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channel does not cause the rejection of a
subsequent START I/O or START I/O FAST
RELEASE but does cause a condition code 1 to be
returned to TEST CHANNEL. The CAl can
therefore be used as a tool for keeping I/O
requests in sequence by using it in conjunction with
TEST CHANNEL. A channel which responded
with condition code 2 because the channel was
busy does not subsequently respond with a
condition code
°
to a TEST CHANNEL without
clearing an interruption condition in the interim.
Priority
0/
Interruptions
Generation of interruption conditions is
asynchronous to the activity in the CPU, and
interruption conditions associated with more than
one I/O device can exist at the same time. The
priority among interruption conditions is controlled
by two types of mechanisms-one establishes the
priority among interruption conditions within a
channel, and another establishes priority among
interruption conditions from different channels. A
channel requests an I/O interruption only after it
has established priority among interruption
conditions. The status associated with interruption
conditions is preserved in the devices or channels
until accepted by the CPU.
Assignment of priority among requests for
interruption associated with devices on anyone
channel is a function of the type of channel, the
type of interruption condition, and the position of
the device on the I/O interface. A device's
position on the interface is not related to its
address. Interruption conditions from different
devices do not necessarily occur in the sequence in
which they are generated. However, multiple
interruption conditions for a single device are
presented in the sequence in which they are
generated.
The priorities among requests for 1/
a
interruptions from different channels depend on
channel addresses. The priorities of channels 1-15
are in the order of their addresses, with channel 1
having the highest priority. The priority of
byte-multiplexer channel
°
is undefined. Its
priority may be above, below, or between those
priorities of channels 1-15.
Interruption Action
An I/O interruption can occur only when the CPU
is enabled for I/O interruptions. The interruption
occurs at the completion of a unit of operation. If
a
channel has established the priority among
12-46
IBM 4300 Processors Principles of Operation
interruption conditions, while the CPU is disabled
for I/O interruptions, the interruption occurs
immediately after the completion of the instruction
enabling the CPU and before the next instruction is
executed. This interruption is associated with the
highest priority condition for the channel. If
interruptions are allowed from more than one
channel concurrently, the interruption occurs from
the channel having the highest priority among those
requesting interruption.
If
the priority among interruption conditions has
not yet been established in the channel by the time
the interruption is allowed, the interruption does
not necessarily occur immediately after the
completion of the instruction enabling the CPU.
This delay can occur regardless of how long the
interruption condition has existed in the device or
the subchannel.
The interruption causes the current program-
status word (PSW) to be stored as the old PSW at
location 56 and causes the CSW associated with
the interruption to be stored at location 64. In EC
mode, the channel and device causing the
interruption are identified by the I/O address
which is stored at locations 186-187. In BC mode,
the channel and device causing the interruption are
identified by the I/O address in bit positions 16-31
of the 1/
a
old PSW.
If
a limited-channel logout is present, it is stored
at locations 176-179.
Subsequently, a new PSW is loaded from
location 120, and processing resumes in the state
indicated by this PSW. The CSW associated with
the interruption identifies the interruption condition
responsible for the interruption and provides
further details about the progress of the operation
and the status of the device.
Programming Note
When a number of I/O devices on a shared control
unit are concurrently executing operations such as
rewinding tape or positioning a disk-access
mechanism, the initial device-end signals generated
on completion of the operations are provided in the
order of generation, unless command chaining is
specified for the operation last initiated. In the
latter case, the control unit provides the device-end
signal for the last initiated operation first, and the
other signals are delayed until the subchannel is
freed. Whenever interruptions due to the
device-end signals are delayed because the CPU is
disabled for 1/
a
interruptions or the subchannel is
busy, the original order of the signals is destroyed.
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