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Program Reset
Program reset causes the following actions:
1. The execution of the current instruction or
other processing sequence, such as an
interruption, is terminated, and all program-
interruption and supervisor-caB-interruption
conditions are cleared.
2.
Any pending external-interruption conditions
are cleared.
3. Any pending machine-check-interruption
conditions, error indications, and check-stop
state are cleared.
4. Any buffers containing prefetchect instructions,
operands, or results due to be stored are
cleared.
5. The CPU is placed in the stopped state after
actions 1-4 have been completed.
6.
I/O-system reset is performed in each channel.
7.
Any ongoing machine-save function is halted,
and any partially altered machine-save
information is made invalid.
Register and storage contents remain unchanged
by program reset. However, if a register or storage
location is being accessed at the time the
program-reset operation is performed, the
subsequent contents of the register or location are
unpredictable.
I
As part of the 1/ a-system reset performed (see
~he
section "I/O-System Reset" in Chapter 12,
"Input/Output Operations"), pending
I/O-interruption conditions are cleared, and system
reset is signaled to all control units and devices
configured to the channel. The effect of system
reset on I/O control units and devices and the
resultant control-unit and device state are described
in the appropriate publication on the control unit or
device. A system reset, in general, resets only
those functions in a shared control unit or device
I
that are associated with the particular channel
signaling the reset.
Program reset is performed when the
system-reset-normal key is activated.
It
is also part
of the initial-program-reset function.
Initial Program Reset
Initial program reset combines the program-reset
functions with the following actions:
1. The contents of the current PSW, CPU timer,
and clock comparator are set to zero.
2.
All assigned control-register positions are set to
their initial values.
Thes.e clearing and initializing functions include
validation.
Setting the current PSW to zero causes the PSW
to assume the BC-mode format. The
instruction-length code and interruption code in the
PSW are unpredictable, because these values are
not retained when a new PSW is introduced.
I nitial program reset is part of the clear-reset
function. It is also part of the
initial-pro gram-loading function when the
load-normal or load-clear key is activated.
Clear Reset
Clear reset combines the initial-program-reset
function with an initializing function which causes
the following actions:
1. The general and floating-point registers are set
to zero.
2. The storage key of every storage page is set to
zero.
3. The page bits of every storage page are set to
zeros.
4. All page frames that had been made
temporarily unavailable by DECONFIGURE
PAGE instructions are made available. (This
excludes frames made permanently unavailable
by maintenance intervention.)
5. The page-capacity, existing-frame-capacity,
available-frame-capacity, and free-frame-
capacity counts are initialized.
6.
Let n be the lesser of AFCC, the current
available-frame-capacity count, and PCC, the
page-capacity count. Then each of n page
frames is assigned to one of the first
n storage
pages, namely those with page addresses 0 to n
minus one. These pages are cleared to zero
bytes and have their page states set to
addressable. Any remaining pages have their
page states set to disconnected.
7. Any previously saved machine-save information
is invalidated.
Validation is included in setting registers and
capacity counts and in clearing storage and page
descriptions.
Clear reset is performed when the system-reset-
clear key is activated. Clear reset is also part of
the power-on-reset function, and part of the
initial-program-Ioading function when performed
upon activating the load-clear key.
Programming Notes
1.
For the program-reset operation not to affect
the contents of fields that are to be left
unchanged, the CPU must not be executing
instructions and must be disabled for aB
interruptions at the time of the reset. Except
for the operation of the time-of-day clock,
interval timer, and CPU timer and for the
possibility of taking a machine-check
Chapter 4. Control
4-23
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