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PSW bit 13 and bits in control register 14. See
Chapter 11, "Machine-Check Handling," for more
detailed information.
Program Interruption
Program interruptions are used to report exceptions
and events which occur during execution of the
program. Exceptions include the improper
specification or use of instructions and data.
Events are detected during monitoring (monitor
events) and program-event recording (PER events).
A program interruption causes the old PSW to be
stored at location 40 and a new PSW to be fetched
from location 104.
The cause of the interruption is identified by the
interruption code. When the old PSW specifies the
EC mode, the interruption code is placed at
locations 142-143, the instruction-length code is
placed in bit positions 5 and 6 of the byte at
location 141 with the rest of the bits set to zeros,
and zeros are stored at location 140. When the old
PSW specifies the BC mode, the interruption code
and the ILC are placed in the old PSW. For some
causes, additional information identifying the
reason for the interruption is stored at locations
144-159 in both the EC and BC modes.
Except for the PER-event condition, the
condition causing the interruption is indicated by a
coded value placed in the rightmost seven bit
positions of the interruption code. Only one
condition at a time can be indicated. Bits 0-7 of
the interruption code are set to zeros.
The PER -event condition is indicated by setting
bit 8 of the interruption code to one, with bits 0-7
set to zeros. When this is the only condition, bits
9-15 are also set to zeros. When a PER -event
condition is indicated concurrently with another
program interruption condition, bit 8 is one, and
the coded value for the other condition appears in
bit positions 9-15.
A program interruption can occur only when the
corresponding mask bit, if any, is one. The
program mask in the PSW permits masking four of
the exceptions, bit 1 in control register 0 controls
whether SET SYSTEM MASK causes a
special-operation exception, bits 16-31 in control
register 8 control interruptions due to monitor
events, and, in the EC mode, masks are provided
for controlling interruptions due to PER events.
When the mask bit is zero, the condition is ignored;
the condition does not remain pending.
6-10
IBM 4300 Processors Principles of Operation
Programming Notes
1. When the new PSW for a program interruption
has a PSW -format error or causes an exception
to be recognized in the process of instruction
fetching, a string of program interruptions takes
place. See the section "Priority of
Interruptions" in this chapter for a description
of how such strings are terminated.
2. Some of the conditions indicated as program
exceptions may be recognized also by anIiO
operation, in which. case the exception is
indicated in the channel-status word.
Program-Interruption Conditions
The following is a detailed description of each
program-interruption condition.
Addressing Exception
An addressing exception is recognized when the
CPU causes a reference to a virtual-storage
location that is not provided. A storage location is
not provided when the page address, bits 8-20 of
the storage address, equals or exceeds the
page-capacity count. An address designating a
storage location that is not provided is referred to
as invalid.
The execution of the instruction is suppressed
when the location of the instruction, including the
location of the target instruction of EXECUTE, is
not provided. Except for some specific instructions
whose execution is suppressed, the operation is
terminated when an operand location is not
provided. For termination, changes may occur only
to result fields, which include the condition code,
registers, and any storage locations that are
provided and that are designated to be changed by
the instruction. Therefore, if an instruction is due
to change only the contents of a field in storage,
and every byte of the field is in a location that is
not provided, the operation is suppressed.
The instructions whose execution is always
suppressed are LOAD PSW, SET CLOCK
COMPARATOR, SET CPU TIMER, SET
SYSTEM MASK, STORE CLOCK
COMPARATOR, STORE CPU ID, STORE CPU
TIMER, STORE THEN AND SYSTEM MASK,
and STORE THEN OR SYSTEM MASK.
When part of an operand location is provided
and part is not, storing may be performed in the
part that is provided.
When the address of any halfword of an
instruction is invalid, the instruction-length code
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