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• A machine-check interruption cannot be taken
because of a storage error in page O.
• Invalid CBC is detected in the page description
for page O.
• An error occurs while a page description is being
updated, leaving the page description in an
inconsistent state.
There may be many other conditions for
particular models when an error may cause check
stop.
When the CPU is in the check-stop state,
instructions and interruptions are not executed, the
interval timer is not updated, and channel
operations may be stopped. The time-of-day clock
is normally not affected by the check-stop state.
The CPU timer mayor may not run in the
check-stop state, depending on the error and the
model. The start key and stop key are not effective
in this state.
The CPU may be removed from the check-stop
state by program reset.
Machine-Check Interruption
A request for a machine-check interruption, which
is made pending as the result of a machine check, is
called a machine-check-interruption condition.
There are two major types of machine-check-
interruption conditions: exigent conditions and
repressible conditions.
Exigent Conditions
Exigent machine-check-interruption conditions are
those in which damage has or would have occurred
such that the current instruction or interruption
sequence cannot safely continue. Exigent
conditions are identified in the machine-check-
interruption code by two bits: instruction-
processing damage and system damage. In addition
to indicating specific exigent conditions, the
system-damage bit is used to report any
malfunction or error which cannot be isolated to a
less severe report.
Repressible Conditions
Repressible machine-check-interruption conditions
are those in which the results of the
instruction-processing sequence have not been
affected. Repressible conditions can be delayed,
until the completion of the current instruction or
even longer, without affecting the integrity of CPU
operation. Repressible conditions are of three
classes: recovery, alert, and repressible damage.
Each class has one or more subclasses.
A malfunction in the CPU, storage, channel, or
operator facilities which has been successfully
corrected or circumvented internally without logical
damage is called a recovery condition. Depending
on the model and the type of malfunction, some or
all recovery conditions may be discarded and not
reported. Recovery conditions that are reported
are grouped in one subclass, system recovery.
A machine-check-interruption condition not
directly related to a machine malfunction is called
an alert condition. The alert conditions are
grouped in two subclasses: degradation and
warning.
A malfunction resulting in an incorrect state of a
portion of the system not directly affecting
sequential CPU operation is called a repressible-
damage condition. Repressible-damage conditions
are divided into three subclasses, according to the
function affected: timing-facility damage, interval-
timer damage, and external damage.
Programming
Notes
1. Even though repressible conditions are usually
reported only at normal points of interruption,
they may also be reported with exigent
machine-check conditions. Thus, if an exigent
machine-check condition causes an instruction
to be abnormally terminated and a
machine-check interruption occurs to report the
exigent condition, any pending repressible
conditions may also be reported. The
meaningfulness of the validity bits depends on
what exigent condition is reported.
2. Classification of a damage condition as
repressible does not imply that the damage is
necessarily less severe than damage classified as
an exigent condition. The distinction is
whether action must be taken as soon as the
damage is detected (exigent) or whether the
CPU can continue processing (repressible).
For a repressible condition, the current
instruction can be completed before taking the
machine-check· interruption if the CPU is
enabled; if the CPU is disabled for machine
checks, the condition can safely be kept
pending until the CPU is again enabled for
machine checks.
For example, the CPU may be disabled for
machine-check interruptions because it is
handling an earlier instruction-processing-
damage interruption. If, during that time, an
I/O operation encounters a storage error, that
condition can be kept pending because it is not
Chapter 11. Machine-Check Handling
11-5
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