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instruction address is updated by two halfword
locations. The PSW containing the invalid value
introduced into the system-mask field is stored as
the old PSW.
When a PSW with one of the above error
conditions is introduced during initial program
loading, the loading sequence is not completed, and
the load indicator remains on.
Late Exception Recognition
For the following conditions, the exception is
recognized as part of the execution of the next
instruction:
• A specification exception is recognized due to an
odd instruction address in the PSW (PSW bit 63
is one).
• An access exception (addressing, page-access, or
protection) is associated with the location
designated by the instruction address or with the
location of the second or third halfword of the
instruction starting at the designated address.
The instruction-length code and instruction
address stored in the program old PSW under these
conditions are discussed in the section, "ILC on
Instruction-Fetching Exceptions" in this chapter.
If
the invalid PSW causes the CPU to be enabled
for a pending 1/0, external, or machine-check
interruption, the corresponding interruption occurs,
and the PSW invalidity is not recognized.
Similarly, the specification or access, exception is
not recognized in a PSW specifying the wait state.
Programming Notes
1. The execution of LOAD PSW, SET SYSTEM
MASK, STORE THEN AND SYSTEM MASK,
and STORE THEN OR SYSTEM MASK is
suppressed on' an addressing or protection
exception, and hence the program old PSW
provides information concerning the program
causing the exception.
2. When the first halfword of an instruction can
be fetched but an access exception is
recognized on fetching the second or third
halfword, the ILC is not necessarily related to
the operation code.
3. If the new PSW introduced by an interruption
contains a PSW-format error, a string of
interruptions occurs. (See the section "Priority
of Interruptions" in this chapter.)
External Interruption
The external interruption provides a means by
which the CPU responds to various signals
originating either from within or from without the
system.
An external interruption causes the old PSW to
be stored at location 24 and a new PSW to be
fetched from location 88.
The source of the interruption is identified in the
interruption code. When the old PSW specifies the
EC mode, the interruption code is stored at
locations 134-135, and zeros are stored at locations
132-133. When the old PSW specifies the BC
mode, the interruption code is placed in bit
positions 16-31 of the old PSW, and the
instruction-length code is unpredictable.
External-interruption conditions are of two
types: those for which an interruption request
condition is held pending, and those for which the
condition directly requests the interruption. Clock
comparator and CPU timer are conditions which
directly request external interruptions. If a
condition which directly requests an external
interruption is removed before the request is
honored, the request does not remain pending, and
no interruption occurs. Conversely, the request is
not cleared by the interruption, and if the condition
persists, more than one interruption may. result
from a single occurrence of the condition.
When several interruption requests for a single
source are generated before the interruption is
taken, and the interruption condition is of the type
which is held pending, only one request for that
source is preserved and remains pending.
An external interruption for a particular source
can occur only when the CPU is enabled for
interruption by that source. The external
interruption occurs at the completion of a unit of
operation. Whether the CPU is enabled for
external interruption is controlled by the external
mask, PSW bit 7, and external subclass mask bits in
control register O. Each source for an external
interruption has a subclass mask' bit assigned to it,
and the source can cause an interruption only when
the external-mask bit is one and the corresponding
subclass-mask bit is one. The use of the subclass-
mask bits does not depend on whether the CPU is
in the EC or BC mode.
When the CPU becomes enabled for a pending
external-interruption condition, the interruption
occurs at the completion of the instruction
execution or interruption that causes the enabling.
More than one source may present a request for
an external interruption at the same time. When
the CPU becomes enabled for more than one
concurrently pending request, the interruption
Chapter 6. Interruptions
6-7
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