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The supervisor-call interruption causes the old
PSW to be stored at location 32 and a new PSW to
be fetched from location 96.
The contents of bit positions 8-15 of
SUPERVISOR CALL are placed in the rightmost
byte of the interruption code. The leftmost byte of
the interruption code is set to zero. The
instruction-length code is 1, unless the instruction
was executed by means of EXECUTE, in which
case the code is 2.
When the old PSW specifies the EC mode, the
interruption code is placed in locations 138-139,
the instruction-length code is placed in bit positions
5 and 6 of the byte at location 137, with the other
bits set to zeros, and zeros are stored at location
136. When the old PSW specifies the BC mode,
the interruption code and instruction-length code
appear in the old PSW.
Priority of Interruptions
During the execution of an instruction, several
interruption-causing events may occur
simultaneously. The instruction may give rise to a
program interruption, a request for an external
interruption may be received, equipment
malfunctioning may be detected, an
I/O-interruption request may be made, and the
restart key may be activated. Instead of the
program interruption, a supervisor-call interruption
might occur; or both can occur if program-event-
recording is active. Simultaneous interruption
requests are honored in a predetermined order.
An exigent machine-check condition has the
highest priority. When it occurs, the current
operation is terminated. Program and
supervisor-call interruptions that would have
occurred as a result of the current operation may be
eliminated. Any pending repressible
machine-check conditions may be indicated with
the exigent machine-check interruption. Every
reasonable attempt is made to limit the side effects
of an exigent machine-check condition, and
requests for I/O and external interruptions
normally remain unaffected.
In the absence of an exigent machine-check
condition, interruption requests existing
concurrently at the end of a unit of operation are
honored, in descending order of priority, as follows:
Supervisor call
Program
Repressible machine check
External
Input/ output
Restart
The processing of multiple simultaneous
interruption requests consists in storing the old
PSW and fetching the new PSW belonging to the
interruption first taken. This new PSW is
subsequently stored without the execution of any
instructions, and the new PSW associated with the
next interruption is fetched. Storing and fetching
of PSWs continues until no more interruptions are
to be serviced. The priority is reevaluated after
each new PSW is loaded. Each evaluation is
performed taking into consideration any additional
interruptions which may have become pending.
Additionally, external and I/O interruptions, as
well as machine-check interruptions due to
repressible conditions, are taken only if the current
PSW at the instant of evaluation indicates that the
CPU is interruptible for the cause.
Instruction execution is resumed using the
last-fetched PSW. The order of executing
interruption subroutines is, therefore, the reverse of
the order in which the PSWs are fetched.
If
the new PSW for a program interruption has
an odd instruction address or causes an access
exception to be recognized, another program
interruption occurs. Since this second interruption
introduces the same unacceptable PSW, a string of
interruptions is established. These program
exceptions are recognized as part of the execution
of the following instruction, and the string may be
broken by an external, I/O, machine-check, or
restart interruption or by the stop function.
If
the new PSW for a program interruption
contains a one in an unassigned bit position of an
EC-mode PSW, another program interruption
occurs. This condition is of higher priority than
restart, I/O, external, or repressible machine-check
conditions, or the stop function, and program reset
has to be used to break the string of interruptions.
A string of interruptions for other interruption
classes can also exist if the new PSW is enabled for
the interruption just taken. These include
machine-check interruptions, external interruptions,
and I/O interruptions due to PCI conditions
generated because of CCWs which form a loop.
Furthermore, a string of interruptions involving
more than one interruption class can exist. For
example, assume that the CPU timer is negative
and the CPU-timer subclass mask is one.
If
the
external new PSW has a one in an unassigned bit
position in the EC mode, and the program new
PSW is enabled for external interruptions, then a
string of interruptions occurs, alternating between
external and program. Even more complex strings
Chapter 6. Interruptions
6-19
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