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NI
[S I]
194 1
o
8
16
20
31
NC
°1(L,B1),02(B2)
[SS]
I
B 1
I
/
/
104 1
L
°1
B2
~~
/
0
8
16
20
32
36
The AND of the first and second operands is
placed in the first-operand location.
47
The connective AND is applied to the operands
bit by bit. A bit position in the result is set to one
if the corresponding bit positions in both operands
contain ones; otherwise, the result bit is set to zero.
For NC, each operand is processed left to right.
When the operands overlap, the result is obtained
as if the operands were processed one byte at a
time and each result byte were stored immediately
after the necessary operand byte is fetched.
For NI, the first operand is one byte in length,
and only one byte is stored.
Resulting Condition Code:
o
Result is zero
1
Result is not zero
2
3
Program Exceptions:
Access (fetch, operand 2, Nand NC; fetch and
store, operand 1, NI and NC)
Programming Notes
1. An example of the use of the AND instruction
is given in Appendix A.
2. The instruction AND may be used to set a bit
to zero.
3. Accesses to the first operand of NI andNC
consist in fetching a first-operand byte from
storage and subsequently storing the updated
value. These fetch and store accesses to a
particular byte do not necessarily occur one
immediately after the other. Thus, the
instruction AND cannot be safely used to
update a location in storage if the possibility
exists that another CPU or a channel may also
be updating the location. An example of this
effect is shown for the instruction OR (01) in
the section "Multiprogramming and
Multiprocessing Examples" in Appendix A.
7-8
IBM 4300 Processors Principles of Operation
BRANCH AND LINK
[RR]
o
8
12
15
BAL
R1,02(X2,B2)
[RX]
145 1
I
R1
I
X2
I
B2
°2
o
8
12
16
20
31
Information from the current PSW, including the
updated instruction address, is loaded as link
information in the general register designated by
R
l'
Subsequently, the instruction address is
replaced by the branch address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, bits
8-31 of the general register designated by R2 are
used as the branch address; however, when the R2
field contains zeros, the operation is performed
without branching. The branch address is
computed before the link information is loaded.
The link information consists of the
instruction-length code (ILC), the condition code
(CC), the program mask bits, and the updated
instruction address, arranged in the following
format:
I I
Prog
ILC CC Mask
Instruction Address
o
2
4
8
31
The instruction-length code is 1 or 2.
Condition Code: The code remains unchanged.
Program Exceptions: None.
Programming Notes
1. An example of the use of BRANCH AND
LINK is given in Appendix A.
2. When the R2 field in the RR format contains
all zeros, the link information is loaded without
branching.
I
3. When BRANCH AND LINK is the target
instruction of EXECUTE, the
instruction-length code is 2.
4. The format and the contents of the link
information do not depend on whether the
(
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