Advertisement
these areas has associated with it a validity bit in
the machine-cheek-interruption code. If, for any
reason, the machine cannot store the proper
information in the field, the associated validity bit
is set to zero.
The following are the five sets of registers and
the locations in storage where their contents are
saved during a machine-check interruption.
Locations
216-223
224-231
352-383
384-447
448-511
Registers
CPU timer
Clock comparator
Floating-point registers
0, 2, 4, 6
General registers 0-15
Control registers 0-15
The information stored for unassigned
control-register positions is unpredictable.
Failing"'Storage Address
When storage error uncorrected or storage-key
error uncorrected is indicated in the
machine-cheek-interruption code, the associated
address, called the failing-storage address, is stored
in bits 8-31 of the word at location 248. Bits 0-7
of that word are set to zeros.
The failing-storage address may be the address
of any location within the page that is in error or
that is associated with the storage key in error.
When an error is detected in more than one
location before the interruption, the failing-storage
address may point to any of the failing locations.
Machine-Check Masking
All machine-check interruptions are under control
of the machine-check mask, PSW bit 13. In
addition, some machine-check conditions are
controlled by subclass masks in control register 14.
The exigent machine-check conditions (system
damage and instruction-processing damage) are
controlled only by the machine-check mask, PSW
bit 13. When PSW bit 13 is one, an exigent
condition causes a machine-check interruption.
When PSW bit 13 is zero, the occurrence of an
exigent machine-check condition causes the CPU to
enter the check-stop state.
The repressible machine-check conditions are
controlled both by the machine-check mask, PSW
bit 13, and by four subclass-mask bits in control
register 14.
If
PSW bit 13 is one and one of the
subclass-mask bits is one, the associated condition
11-12
IBM 4300 Processors Principles of Operation
initiates a machine-check interruption.
If
a
subclass-mask bit is zero, the associated condition
does not initiate an interruption. However, when a
machine-check interruption is initiated because of a
condition for which the CPU is enabled, those
conditions for which the CPU is not enabled may
be presented along with the condition which
initiates the interruption. All conditions presented
are then cleared.
Control Register 14
I~~~~I
0 4 7
Bits 4-7 of control register 14 are the subclass
masks for repressible machine-check conditions. In
addition, bit 0 is initialized to one, but it is
otherwise ignored by the machine. All other bits of
control register 14 are unassigned.
Programming Note
The program should avoid, whenever possible,
operating with PSW bit 13, the machine-check
mask, set to zero, since any exigent machine-check
condition which is recognized during this situation
will cause the CPU to enter the check-stop state.
In particular, the program should avoid issuing I/O
instructions or allowing for I/O interruptions with
PSW bit 13 a zero.
Recovery-Report Mask
Bit 4 (RM) of control register 14 controls system-
recovery-interruption conditions. This bit is
initialized to zero.
Degradation-Report Mask
Bit 5 (DM) of control register 14 controls
degradation-interruption conditions. This bit is
initialized to zero.
External-Damage-Report Mask
Bit 6 (EM) of control register 14 controls
timing-facility-damage, interval-timer-damage, and
external-damage conditions. This bit is initialized
to one.
Warning Mask
Bit 7 (WM) of control register 14 controls warning
conditions. This bit is initialized to zero.
Advertisement
Chapters
