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SET SYSTEM MASK
o
8
16
20
31
Bits 0-7 of the current PSW are replaced by the
byte at the location designated by the
second-operand address.
When the SSM-suppression bit, bit 1 of control
register 0, is one and the CPU is in the supervisor
state, a special-operation exception is recognized,
and the operation is suppressed.
The operation is suppressed on protection and
addressing exceptions.
The value to be loaded into the PSW is not
checked for validity before loading. However,
immediately after loading, a specification exception
is recognized, and a program interruption occurs, if
the CPU is in EC mode and the contents of bit
positions
°
and 2-5 of the PSW are not all zeros.
In this case, the instruction is completed, and the
instruction-length code is set to 2. The
specification exception in this case is considered to
be caused as part of the execution of the
instruction.
Bits 8-15 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Privileged Operation
Special Operation
Specification
Programming Note
The SSM instruction is frequently used in the BC
mode to disable or enable the CPU for IIO or
external interruptions. Hence, suppressing the
execution of the SSM instruction by means of the
SSM -suppression bit, bit 1 of control register 0,
may be useful when converting a program written
for aBC-mode PSW to operate with an EC-mode
PSW.
STORE CAPACITY COUNTS
IB21FI
o
16
20
31
The current values of the page-capacity (PCC),
existing-frame-capacity (EFCC),
available-frame-capacity (AFCC), and free-frame-
capacity (FFCC) counts are stored at the 16-byte
location designated by the second-operand address.
The counts are stored as 32-bit unsigned binary
integers in the order, from left to right, of PCC,
EFCC, AFCC, and FFCC.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Privileged Operation
Programming Notes
1. The instruction allows the program to display
the current values of the PCC, EFCC, AFCC,
and FFCC for initialization purposes at IPL
time and for the management of virtual storage
and machine storage.
2. The high-order 16 bits of each counter value,
as stored, are always zeros. The counter values
cannot exceed 65,535.
STORE CLOCK COMPARA.TOR
IB207
1
o
16
20
31
The current value of the clock comparator is stored
at the doubleword location designated by the
second-operand address.
Zeros are provided for the rightmost bit positions
of the clock comparator that are not compared with
the time-of-day clock.
The operand must be designated on a
doubleword boundary; otherwise, a specification
exception is recognized, and the operation is
suppressed. The operation is suppressed on
addressing and protection exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Privileged Operation
Specification
Chapter 10. Control Instructions
10-11
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