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designate an even-numbered register. When Rl is
odd, a specification exception is recognized.
The second-operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
All 64 bits of the first operand participate in the
shift. Bits shifted out of bit position 31 of the
odd-numbered register are not inspected and are
lost. Zeros are supplied to the vacated register
positions on the left.
Condition Code: The code remains unchanged.
Program Exceptions:
S pecifica tion
SHIFT RIGHT SINGLE
SRA
R1,02(B2)
[RS]
o
8
12
16
20
31
The numeric part of the first operand is shifted
right the number of bits specified by the
second -operand address. Bits 12-15 of the
instruction are ignored.
The second-operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
The first operand is treated as a 32-bit signed
binary integer. The sign of the first operand
remains unchanged. All 31 numeric bits of the
operand participate in the right shift. Bits shifted
out of bit position 31 are not inspected and are
lost. Bits equal to the sign are supplied to the
vacated register positions on the left.
Resulting Condition Code:
o
Result is zero
1
Result is less than zero
2
Result is greater than zero
3
Program Exceptions: None.
Programming Notes
1. A right shift of one bit position is equivalent to
division by 2 with rounding downward. When
an even number is shifted right one position,
the result is equivalent to dividing the number
by 2. When an odd number is shifted right one
position, the result is equivalent to dividing the
next lower number by 2. For example, +5
shifted right by one bit position yields + 2,
whereas -5 yields -3.
2. Shift amounts from 31 to 63 cause the entire
numeric part to be shifted out of the register,
leaving a result of -1 or zero, depending on
whether or not the initial contents were
negative.
SHIFT RIGHT SINGLE LOGICAL
SRL
'88'
°2
o
8
12
16
20
31
The first operand is shifted right the number of bits
specified by the second-operand address. Bits
12-15 of the instruction are ignored.
The second-operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
All 32 bits of the first operand participate in the
shift. Bits shifted out of bit position 31 are not
inspected and are lost. Zeros are supplied to the
vacated register positions on the left.
Condition Code: The code remains unchanged.
Program Exceptions: None.
STORE
, 50'
I
R 1
I
X2
I
B2
02
o
8
12
16
20
31
The first operand is stored at the second-operand
location.
The 32 bits in the general register are placed
unchanged at the second-operand location.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Chapter 7. General Instructions
7-31
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