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considered as a contiguous field and are compared
with the second operand. The second operand is a
contiguous field in storage, starting at the
second-operand address and equal in length to the
num ber of ones in the mask. The bytes in the
general register corresponding to zeros in the mask
do not participate in the operation.
I
The comparison proceeds left to right, byte by
byte, and ends as soon as an inequality is found or
the end of the fields is reached.
When the mask is not zero, exceptions associated
with storage-operand access are recognized for no
more than the number of bytes specified by the
mask. Access exceptions mayor may not be
recognized for the portion of a storage operand to
the right of the first unequal byte. When the mask
is zero, access exceptions are recognized for one
byte.
Resulting Condition Code:
o
Selected bytes are equal, or mask is zero
1
Selected field of first operand is low
2
Selected field of first operand is high
3
Program Exceptions:
Access (fetch, operand
2)
Programming Note
An example of the use of COMPARE LOGICAL
CHARACTERS UNDER MASK is given in
Appendix A.
COMPARE LOGICAL LONG
[RR]
o
8
12
15
The first operand is compared with the second
operand, and the result is indicated in the condition
code. The shorter operand is considered to be
extended on the right with padding bytes.
The Rl and R2 fields each specify an even-odd
pair of'general registers and must designate an
even-numbered register; otherwise, a specification
exception is recognized.
The location of the leftmost byte of the first
operand and second operand is designated by bits
8-31 of the general registers specified by the Rl
and R2 fields, respectively. The number of bytes in
7-14
IBM 4300 Processors Principles of Operation
the first-operand and second-:operand locations is,
specified by bits 8-31 of general registers Rl
+
1
and R2
+
1, respectively. Bit positions 0-7. of
register R 2
+
1 contain the padding byte. The
contents of bit positions 0-7 of registers R
1,
R
2 ,
and R
1
+
1 are ignored.
Graphically, the contents of the registers just
described are as follows:
R1
I11111111I
First-Operand Address
o
8
31
R1+1
11/1111/11
First-Operand Length
o
8
31
R2
I11111111I
Second-Operand Addressl
o
8
31
I
Second-Operand Length
I
8
31
The comparison proceeds left to right, byte by
byte, and ends as soon as an inequality is found or
the end of the longer operand is reached. If the
operands are not of the same length, the shorter
operand is considered to be extended on the right
with the appropriate number of padding bytes.
If
both operands are of zero length, the operands
are considered to be equal.
The execution of the instruction is interruptible.
When an interruption occurs, other than one that
causes termination, the contents of registers R
1
+
1
and R2
+
1 are decremented by the number of bytes
compared, and the contents of registers R
1
and R2
are incremented by the same number, so that the
instruction, when reexecuted, resumes at the point
of interruption. The high-order bits which are not
part of the address in registers R
1
and R2 are set to
zeros; the contents of the high-order byte of
registers Rl
+
1 and R 2
+
1 remain unchanged; and
the condition code is unpredictable.
If
the
operation is interrupted after the shorter operand
has been exhausted, the length field pertaining to
the shorter operand is zero, and its address is
updated accordingly.
If
the operation ends because of an inequality,
the address fields in registers R
1
and R2 at
completion identify the first unequal byte in each
operand. The lengths in bit positions 8-31 of
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