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registers R
1
+
1 and R2
+
1 are decremented by the
number of bytes that were equal, unless the
inequality occurred with the padding byte, in which
case the length field for the shorter operand is set
to zero. The addresses in registers Rl and R2 are
incremented by the amounts by which the
corresponding length fields were reduced.
If
the two operands, including the padding byte,
if necessary, are equal, both length fields are made
zero at completion, and the addresses are
incremented by the corresponding operand-length
values. The bits which are not part of the address
in registers R
1
and R2 are set to zeros, including
the case when one or both of the initial length
values are zero. The contents of bit positions 0-7
of registers R
1
+
1 and R2
+
1 remain unchanged.
Access exceptions for the portion of a storage
operand to the right of the first unequal byte may
or may not be recognized. For operands longer
than 2,048 bytes, access exceptions are not
recognized more than 2,048 bytes beyond the byte
being processed. Access exceptions are not
indicated for locations more than 2,048 bytes
beyond the first unequal byte.
When the length of an operand is zero, no access
exceptions are recognized for that operand. Access
exceptions are not recognized for an operand if the
R field associated with that operand is odd.
Resulting Condition Code:
o
Operands are equal, or both have zero length
1
First operand is low
2
First operand is high
3
Program Exceptions:
Access (fetch, operands 1 and 2)
Specification
Programming Notes
1. An example of the use of COMPARE
LOGICAL LONG is given in Appendix A.
2. When the R
1
and R2 fields are the same, the
operation proceeds in the same way as when
two distinct pairs of registers having the same
contents are specified, and, in the absence of
dynamic modification of the operand area by
another CPU or a channel, condition code 0 is
set. However, it is unpredictable whether
access exceptions are recognized for the
operand since the operation can be completed
without storage being accessed.
3. Other programming notes concerning
interruptible instructions are included in the
section "Interruptible Instructions" in Chapter
5, "Program Execution."
4. Special precautions should be taken when
COMPARE LOGICAL LONG is made the
target of EXECUTE. See the programming
note concerning interruptible instructions under
EXECUTE.
CONVERT
TO
BINARY
eVB
R1,02(X2,B2)
[RX]
'4F'
I
R1
I
X2
I
B2
°2
0
8
12
16
20
31
The radix of the second operand is changed from
decimal to binary, and the result is placed in the
first-operand location.
The second operand occupies eight bytes in
storage and is treated as packed decimal data, as
described in Chapter 8, "Decimal Instructions."
It
is checked for valid sign and digit codes, and a data
exception is recognized when an invalid code is
detected.
The result of the conversion is a 32-bit signed
binary integer, which is placed in the general
register specified by R
1 .
The maximum positive
number that can be converted and still be
contained in a 32-bit register is 2,147,483,647; the
maximum negative number (the negative number
with the greatest absolute value) that can be
converted is -2,147,483,648. For any decimal
number outside this range, the operation is
completed by placing the 32 low-order bits of the
binary result in the register, and a fixed-point-
divide exception is recognized.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Data
Fixed-Point Divide
Programming Notes
1.
An example of the use of CONVERT TO
BINARY is given in Appendix A;
2. When the second operand is negative, the result
is in two's-complement notation.
Chapter 7. General Instructions
7-15
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