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R
PM User I/O Pins
Table 2-48: PM1 Pinout
FPGA
PM1 Pin
Pin (U37)
A1
AL9
A2
AK9
A3
AD14
A4
AC13
A5
AA8
A6
AA9
A7
Y6
A8
AA6
A9
AL3
A10
AM3
A11
AK14
A12
AL14
A13
F1
A14
G1
A15
AL1
A16
AM1
A17
U1
A18
V1
A19
AP11
A20
AP12
C1
AB11
C2
AA11
C3
AC3
C4
AC4
C5
Y9
C6
W9
C7
AG7
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from
Elcodis.com
electronic components distributor
PM1 User I/O
The PM1 connector makes the MGT signals from the eight RocketIO transceivers available
to the user, along with LVDS pairs and single-ended signals.
for the PM1 connector.
Pin Description
IO_L10P_8
IO_L10N_8
IO_L7P_8
IO_L7N_8
IO_L13N_12
IO_L13P_12
IO_L10N_12
IO_L10P_12
IO_L26N_12
IO_L26P_12
IO_L31P_8
IO_L31N_8
RXPPADB_113
RXNPADB_113
RXPPADB_110
RXNPADB_110
TXPPADB_112
TXNPADB_112
TXPPADB_109
TXNPADB_109
IO_L1P_8
IO_L1N_8
IO_L14N_12
IO_L14P_12
IO_L12N_VREF_12
IO_L12P_12
IO_L27N_12
ML410 Schematic
FPGA Bank
Net
V
CCO
PM_IO_94
2.5V
PM_IO_95
2.5V
PM_IO_86
2.5V
PM_IO_87
2.5V
PM_IO_3V_25
3V
PM_IO_3V_18
3V
PM_IO_3V_7
3V
PM_IO_3V_22
3V
PM_IO_3V_9
3V
PM_IO_3V_13
3V
PM_IO_82
2.5V
PM_IO_83
2.5V
RXPPADB_110
RXNPADB_110
RXPPADB_110
RXNPADB_110
TXPPADB_112
TXNPADB_112
TXPPADB_109
TXNPADB_109
PM_IO_90
2.5V
PM_IO_91
2.5V
PM_IO_3V_16
3V
PM_IO_3V_12
3V
PM_IO_3V_1
3V
PM_IO_3V_3
3V
PM_IO_3V_17
3V
www.xilinx.com
High-Speed I/O
Table 2-48
shows the pinout
Pin Function
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
MGT RX pair received by host
FPGA
MGT RX pair received by host
FPGA
MGT TX pair driven by host
FPGA
MGT TX pair driven by host
FPGA
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
89
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