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IIC/SMBus Interface
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Table 2-34: ALi M1535D+ Flash Memory Interface (Cont'd)
Schematic Net
Name
ROM_A14
ROM_A13
ROM_A12
ROM_A11
ROM_A10
ROM_A9
ROM_A8
ROM_A7
ROM_A6
ROM_A5
ROM_A4
ROM_A3
ROM_A2
ROM_A1
ROM_A0
Introduction to IIC/SMBus
The Inter Integrated Circuit (IIC) bus provides the connection from the CPU to peripherals.
It is a serial bus with a data signal, SDA, and a clock signal, SCL, both of which are
bidirectional. The IIC/SMBus interface serves as an interface to one master device and
multiple slave devices. The interface operates in the range of 100 kHz to 400 kHz.
The SMBus also provides connectivity from the CPU to peripherals. The SMBus is also a
two wire serial bus through which simple power related devices can communicate with
the rest of the system. SMBus uses IIC as its backbone. EDK provides IP that integrates the
IIC interface with a microprocessor system. See the EDK Processor IP User Guide
more details.
IIC/SMBus Signaling
The IIC bus data and clock signals operate as open-drain. By default, these signals are
pulled High to 5V, although some devices support lower voltages. Either the master device
or a slave device can drive either of the signals Low to transmit data or clock signals.
M1535D+ Pin
AM29F040B Pin
(U15)
(U4)
T16
5
U16
4
V16
12
W16
1
Y16
31
R17
2
T17
3
U17
13
V17
14
W17
15
Y17
16
V18
17
W18
18
Y18
19
V19
20
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Detailed Description
Description
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