Xilinx ML410 User Manual page 33

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Table 2-5 describes all the signals associated with DDR2 DIMM component memories.
Note that the DDR2_DQ signal names do not correlate because the FPGA uses IBM
notation, big endian, while the DDR2 DIMM uses Intel notation, little endian.
Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48)
UCF Signal Name
DDR2_WE_N
DDR2_CAS_N
DDR2_RAS_N
DDR2_RST_N
DDR2_ODT
DDR2_LOOP (Bank 9)
DDR2_LOOP (Bank 11)
DDR2_DQSn[0]
DDR2_DQS[0]
DDR2_DQSn[1]
DDR2_DQS[1]
DDR2_DQSn[2]
DDR2_DQS[2]
DDR2_DQSn[3]
DDR2_DQS[3]
DDR2_DQSn[4]
DDR2_DQS[4]
DDR2_DQSn[5]
DDR2_DQS[5]
DDR2_DQSn[6]
DDR2_DQS[6]
DDR2_DQSn[7]
DDR2_DQS[7]
DDR2_A[0]
DDR2_A[1]
DDR2_A[2]
DDR2_A[3]
DDR2_A[4]
DDR2_A[5]
DDR2_A[6]
www.xilinx.com
XC4FX60 Pin Schematic Signal
(U37) Name
T31 DDR2_WE_N
R31 DDR2_CAS_N
R32 DDR2_RAS_N
AA26 DDR2_RST_N
AA25 DDR2_ODT
M26
AB26
E29 DDR2_DQS[00]
F29 DDR2_DQS[00]
J29 DDR2_DQSn[01]
K29 DDR2_DQS[01]
P26 DDR2_DQSn[02]
P27 DDR2_DQS[02]
N32 DDR2_DQSn[03]
P32 DDR2_DQS[03]
V27 DDR2_DQSn[04]
W27 DDR2_DQS[04]
W30 DDR2_DQSn[05]
W31 DDR2_DQS[05]
AH32 DDR2_DQSn[06]
AG32 DDR2_DQS[06]
AE31 DDR2_DQSn[07]
AE32 DDR2_DQS[07]
H28 DDR2_A[00]
K28 DDR2_A[01]
L28 DDR2_A[02]
M25 DDR2_A[03]
Y24 DDR2_A[04]
N27 DDR2_A[05]
AD26 DDR2_A[06]
Detailed Description
DDR2 DIMM
(P48)
73
74
192
18
195
- -
- -
6
7
15
16
27
28
36
37
83
84
92
93
104
105
113
114
188
183
63
182
61
60
180
33