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Xilinx Virtex-4 ML455 User Manual

Xilinx Virtex-4 ML455 User Manual

Pci/pci-x development kit
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Virtex-4 ML455
PCI/PCI-X
Development Kit
User Guide
UG084 (v1.0) May 17, 2005
R
www.BDTIC.com/XILINX

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Summary of Contents for Xilinx Virtex-4 ML455

  • Page 1 Virtex-4 ML455 PCI/PCI-X Development Kit User Guide UG084 (v1.0) May 17, 2005 www.BDTIC.com/XILINX...

  • Page 2: Revision History

    Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.

  • Page 3: Table Of Contents

    Xilinx Documents ........
  • Page 4 Specifying the Xilinx PROM Device ........

  • Page 5: Chapter 1: Introduction

    3.3V 64-bit Connector 5V 64-bit Connector ug084_c1_01_050605 Figure 1-1: Add-in Card Connectors The ML455 board is supported by Xilinx PCI and PCI-X LogiCORE versions 3.0 and 5.0, respectively. Table 1-1 lists the Xilinx PCI and PCI-X cores. Table 1-1: Xilinx PCI and PCI-X Cores...
  • Page 6 • JTAG cable, Xilinx Parallel Cable IV, or Xilinx Platform Cable USB For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com. The heart of the kit is the ML455 board. This manual provides comprehensive information on this board.

  • Page 7: Virtex-4 Ml455 Board

    33 MHz LVCMOS • One DB9-M RS232 port (serial cable not provided) • Support for up to four FPGA design images in a Xilinx XCF32P-FSG48C Platform Flash configuration PROM • Static or dynamic device reconfiguration support with the XC2C32 CoolRunner™ II CPLD •...
  • Page 8 Chapter 1: Introduction Figure 1-2 shows the ML455 board. Figure 1-2: Virtex-4 ML455 Board www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 9: Chapter 2: Getting Started

    Documentation and Reference Design CD The CD included in the Virtex-4 ML455 board kit contains the board design files for the ML455 board, including schematics, PCB layout, and bill of materials. Open the ReadMe.txt file on the CD to review the list of contents.
  • Page 10 Chapter 2: Getting Started www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 11: Chapter 3: Hardware Description

    Chapter 3 Hardware Description A high-level block diagram of the Virtex-4 ML455 board is shown in Figure 3-1, followed by a brief description of each board section. 128 MByte User Switches SODIMM (J4) User 200 MHz LEDs LVPECL Oscillator Parallel Cable IV...
  • Page 12 16 I/Os, 12 used J4 DDR SODIMM Socket I/F Socket I/F = 2.5V User SW and LED I/F 133M, 200M Osc I/F UG084_c3_08_042605 Figure 3-2: Virtex-4 XC4VLX25FF668 Banking (Top View) www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 13: Clock Generation

    The PCI specification calls for the PCI bus clock, sourced from the motherboard PCI slot, to have one load on the add-in cards. The Xilinx PCI and PCI-X IP cores, depending upon bus mode and frequency, require that the PCI bus clock enter the FPGA on a specific clock pin...

  • Page 14: Ddr Sdram Sodimm Memory

    The ML455 board contains a 200-pin, small-outline dual in-line memory module (SODIMM) connector (J4) that supports installation of DDR SDRAM SODIMM memory modules of 128 MB, 256 MB, 512 MB, or 1 GB. Xilinx provides a 128 MB memory SODIMM Micron Semiconductor part number MT8VDDT1664HDG-265B3, with the kit.
  • Page 15 DQ56 DQ25 AD26 DQ57 DQ26 AC22 DQ58 DQ27 AB22 DQ59 DQ28 AA19 DQ60 DQ29 AA20 DQ61 DQ30 AA17 DQ62 DQ31 AB20 DQ63 DQ32 DQS0 DQ33 DQS1 DQ34 DQS2 AB25 www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...

  • Page 16: User Leds

    (Q1). Refer to schematic sheet 15. Table 3-4 lists the FPGA pin assignments. Table 3-4: Configuration INIT and DONE LED Pin Assignments FPGA Pin Number Designation (FF668 Package) FPGA_INIT D5 INIT FPGA_DONE D6 DONE www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 17: User Push-Button Switches

    MAX3316 connector (P4) RS232 interface signals a nominal ± 4V swing up to 460 kb/s data rate. The user must provide a UART core internal to the FPGA to enable serial communication. www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 18 Figure 3-3: RS232 Interface Block Diagram The RS232 DB9-F to DB9-F cable is not included in the kit. A NULL modem DB9-F to DB9-F serial cable is required for ML455 to PC serial communications. www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 19: General-Purpose I/O And Lcd Header

    P11 Pin # FPGA Pin # GP Mode LCD Mode VCC or GND no connect VCC or GND no connect test1 LCD_DRIVE test2 LCD_DATA7 test3 LCD_DATA6 test4 LCD_DATA5 test5 LCD_DATA4 www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...

  • Page 20: Power Consumption

    PCI edge connector pinout). The ML455 board on-board power rails are 5.0V, 3.3V, 3.0V, 2.5V, 1.8V, 1.2V, and 1.25V. Table 3-9 lists the voltages. www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 21: Voltage Regulator Circuit Descriptions

    LT1764A 5-pin linear 3A capable voltage regulators (U2, U3, and U4), which have the same basic topology. The output adjust resistor is calculated from the formula given in the Linear Technology data sheet (part number LT1764AF) at www.linear-tech.com): www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 22 1. The LT1764A minimum voltage out is 1.21V, achieved with no adjust resistor network. Adj pin 5 is = 1.21V, this regulator cannot be adjusted ± 5%. wired to V pin 4. Because the minimum V www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 23: Lt1763Cs88 Voltage Regulator

    LT1764AEQ (U3) voltage regulator, set at 3.0V. This regulator sources to U10 LX25 Banks 6 and 10, the PCI edge connector interface banks. The following Xilinx application notes provide PCI interface designs using Xilinx devices: • XAPP646: “Connecting Virtex-II Devices to a 3.3V/5V PCI Bus”...

  • Page 24: Ddr Memory Bus Termination Module

    Table 3-11: P1 PCI Edge Connector Pinout P1 A Side Signal P1 B Side Signal 32-Bit Connector unused VCC_MINUS12 VCC12 unused unused EDGE_JTAG EDGE_JTAG VCC5 VCC5 EDGE_INTA_B VCC5 EDGE_INTC_B EDGE_INTB_B VCC5 EDGE_INTD_B www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 25 EDGE_AD27 EDGE_AD25 EDGE_AD24 VCC3V3 EDGE_IDSEL EDGE_CBE3 VCC3V3 EDGE_AD23 EDGE_AD22 EDGE_AD20 EDGE_AD21 EDGE_AD19 EDGE_AD18 VCC3V3 EDGE_AD16 EDGE_AD17 VCC3V3 EDGE_CBE2 EDGE_FRAME_B EDGE_IRDY_B EDGE_TRDY_B VCC3V3 EDGE_DEVSEL_B EDGE_STOP_B EDGE_PCIXCAP VCC3V3 unused unused EDGE_PERR_B www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 26 EDGE_AD5 EDGE_AD3 EDGE_AD2 EDGE_AD0 EDGE_AD1 VCC3V3 VCC3V3 EDGE_REQ64_B EDGE_ACK64_B VCC5 VCC5 VCC5 VCC5 64-Bit Connector unused EDGE_CBE7 EDGE_CBE5 EDGE_CBE6 VCC3V3 EDGE_CBE4 EDGE_PAR64 EDGE_AD62 EDGE_AD63 EDGE_AD61 EDGE_AD60 VCC3V3 EDGE_AD58 EDGE_AD59 www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 27 PCI signal names. The ML455 board supports both PCI and PCI-X applications. The edge connector interfaces with the system board connector. Xilinx has both PCI and PCI-X LogiCORE intellectual property cores available to facilitate getting started with application specific design.

  • Page 28: Ml455 Board Implementation

    No jumper shunt across P8 indicates that the card is PCI-X 133 capable. • A jumper shunt across P8 pins 2 and 3 indicates that the card is not PCI-X capable (i.e., is PCI, not PCI-X). www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 29: 64-Bit Pci Socket (Top Of The Ml455 Board)

    3.3V KEY 3.3V KEY 3.3V KEY VCC3V3 unused SKT_RST_O_B VCC3V3 CLK_TO_SOCKET SKT_GNT_I_B SKT_REQ_O_B SKT_PME_O_B VCC3V3 SKT_AD30 SKT_AD31 VCC3V3 SKT_AD29 SKT_AD28 SKT_AD26 SKT_AD27 SKT_AD25 SKT_AD24 VCC3V3 SKT_IDSEL SKT_CBE3_B VCC3V3 SKT_AD23 SKT_AD22 www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 30 SKT_SERR_B SKT_PAR VCC3V3 SKT_AD15 SKT_CBE1_B VCC3V3 SKT_AD14 SKT_AD13 SKT_AD11 SKT_AD12 SKT_AD10 SKT_AD9 SKT_M66EN SKT_CBE0_B SKT_AD8 VCC3V3 SKT_AD7 SKT_AD6 VCC3V3 SKT_AD4 SKT_AD5 SKT_AD3 SKT_AD2 SKT_AD0 SKT_AD1 VCC3V3 VCC3V3 SKT_REQ64_B SKT_ACK64_B www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 31 SKT_AD56 SKT_AD54 SKT_AD55 VCC3V3 SKT_AD53 SKT_AD52 SKT_AD50 SKT_AD51 SKT_AD49 SKT_AD48 VCC3V3 SKT_AD46 SKT_AD47 SKT_AD45 SKT_AD44 SKT_AD42 SKT_AD43 VCC3V3 SKT_AD41 SKT_AD40 SKT_AD38 SKT_AD39 SKT_AD37 SKT_AD36 VCC3V3 SKT_AD34 SKT_AD35 SKT_AD33 SKT_AD32 www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...

  • Page 32: Xc2C32 Coolrunner-Ii Cpld U6

    P3. In concert with the XC2C32 CPLD, the XCF32PFS48C supports static and dynamic reconfiguration of the FPGA. Chapter 4, “Configuration,” provides more details concerning the ML455 board configuration. www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 33: Reference Documents

    Phone: 800-433-5177 (inside the U.S.), 503-291-2569 (outside the U.S.) Fax: 503-297-1090 e-mail: administration@pcisig.com Website: http://www.pcisig.com • PCI Local Bus Specification, Revision 3.0 • PCI-X Addendum to the PCI Local Bus Specification www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 34 Chapter 3: Hardware Description www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 35: Configuration Modes

    Chapter 4 Configuration The Virtex-4 ML455 board includes several options to configure the XC4VLX25 Virtex-4 FPGA, XC2C32 CoolRunner-II CPLD, and the XCF32PF Platform Flash. The basic configuration modes for the Virtex-4 family are: • JTAG mode via Parallel Cable IV or equivalent •...

  • Page 36: Jtag Chain

    XCF32PF UG084_c4_02_050705 Figure 4-2: JTAG Chain JTAG Port The Virtex-4 ML455 board provides a JTAG connector (P5) to configure the Virtex-4 FPGA and program JTAG devices located in the JTAG chain. Figure 4-3 shows the pin assignments for the JTAG connector. The JTAG cable connects to P5 as shown in Figure 4-4.
  • Page 37 Description Name Number Number Number Number JTAG_TMS JTAG TMS to FPGA/CPLD/ FLASH JTAG_TCK JTAG TCK to FPGA/CPLD/ FLASH JTAG_TDO JTAG TDO from FLASH JTAG_TDI JTAG TDI to FPGA TDI www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...

  • Page 38: Selectmap Interface

    12 8 2 3 13 33 MHz From/To P2 CPLD DIP SW UG084_c4_05_050705 Notes: 1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os. Figure 4-5: Schematic of Flash/CPLD/FPGA SelectMAP Interface www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 39 1. The Net Names and Directions for pins F13, F12, F11, and F16 were chosen to support a specific PCI/PCI-X design as described below in “CPLD Programming Examples.” The user can use these pins as spare, bidirectional pins. 2. Use LVCMOS_25 I/O standard for general-purpose I/O connected to the CPLD. www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 40 Spare I/O connected to FPGA pin D13 CPLD_SPARE3 Spare Input connected to FPGA pin D15 CPLD_SPARE4 IO10 Spare I/O connected to FPGA pin E14 CPLD_SPARE5 IO11 Spare I/O connected to FPGA pin C11 www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 41 SelectMAP data bit 4 connected to FPGA FLASH_D5 SelectMAP data bit 5 connected to FPGA FLASH_D6 SelectMAP data bit 6 connected to FPGA FLASH_D7 SelectMAP data bit 7 connected to FPGA www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 42 DNC6 Do Not Connect Unused DNC7 Do Not Connect Unused DNC8 Do Not Connect Unused DNC9 Do Not Connect Unused DNC10 Do Not Connect Unused DNC11 Do Not Connect www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...

  • Page 43: Cpld Programming Examples

    1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os. Figure 4-6: CPLD Configuration for Static Configuration Table 4-6: Bitstream Selection Setting for Header P3 Bitstream Revision Jumper Settings for P3 1-2 and 3-4 None www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...

  • Page 44: Generic Dynamic Reconfiguration

    The MAN_AUTO_B input to the CPLD can be incorporated into the design to override the dynamic reconfiguration and allow only static configuration as described in XAPP693: A CPLD-Based Configuration and Revision Manager from Xilinx Platform Flash PROMs and FPGAs. This application note provides details on using a CPLD and Platform Flash to dynamically reconfigure an FPGA.

  • Page 45: Selectmap Clock Selection

    Online documentation from the Configuration File Wizard and iMPACT is available through the Help -> Help Topics menu selection in iMPACT. Chapter 16 of the Xilinx Development System Reference Guide provides details on how to create a PROM image file using PROMGen.

  • Page 46: Setup

    Under Prepare PROM Files, shown in Figure 4-9, select the following: ♦ Select the Xilinx PROM with Design Revisioning Enabled radio button. ♦ Under PROM File Format, select the MCS radio button. ♦ In the PROM File Name box, enter a filename of your choice.

  • Page 47: Specifying The Xilinx Prom Device

    Platform Flash Image Generation and Programming Specifying the Xilinx PROM Device Follow these steps to specify the PROM device: Under Specify Xilinx PROM Device, shown in Figure 4-10, select the following: ♦ From the Select a PROM drop-down boxes, choose xcfp and xcf32p, then click Add.

  • Page 48: Programming The Prom

    Chapter 4: Configuration 12. Under PROM File Generation → Do you want to generate…now?, click Yes. 13. Under Xilinx iMPACT → Do you want to compress file?, click No. 14. After a pause, PROM File Generation Succeeded is displayed. A PROM image file is now created and is ready for programming into the ML455 board. A fully populated PROM file (.mcs) with all 4 revisions must always be generated even if all...
  • Page 49 Platform Flash Image Generation and Programming UG084_c4_11_022705 Figure 4-11: Programming the PROM www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 50 Chapter 4: Configuration www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board UG084 (v1.0) May 17, 2005...
  • Page 51 U10 pin on the Virtex-4 FPGA on the ML455 board. The operation is at 133 MHz. The mother board is the Xilinx ML310, which has a 13-inch clock trace with series and parallel resistors. For this simulation, the series R was set to 0 ohms, and the parallel termination to GND was set to open.
  • Page 52 1500.0 1000.0 500.0 0.000 500.0 0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000 Time (ns) UG084_apx_03_051005 Figure A-3: Both Jumpers in Place (R2 and R242) www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Development Kit UG084 (v1.0) May 17, 2005...
  • Page 53 500.0 0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000 Time (ns) UG084_apx_05_051105 Figure A-5: Bottom Jumper is a Transmission Line (Hard Routed through the Net) www.BDTIC.com/XILINX Virtex-4 ML455 PCI/PCI-X Development Kit www.xilinx.com UG084 (v1.0) May 17, 2005...
  • Page 54 500.0 0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000 Time (ns) UG084_apx_06_051105 Figure A-6: Top and Bottom Jumpers are Transmission Lines (Hard Routed through Nets) www.BDTIC.com/XILINX www.xilinx.com Virtex-4 ML455 PCI/PCI-X Development Kit UG084 (v1.0) May 17, 2005...

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