Tri-Mode (10/100/1000 Mb/S) Ethernet Phy - Xilinx ML410 User Manual

R
System Clk
DDR Device
External Clk

Tri-Mode (10/100/1000 Mb/s) Ethernet PHY

ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Figure 2-5 is a block diagram of the DDR2 DIMM interface.
FPGA (U37)
CLKIN CLK0
CLKFB CLK90
CLKDV
DCM
IDELAYCTRL
200 MHz Clk REFCLK
Figure 2-5: DDR2 DIMM Block Diagram
ML410 platforms feature two Ethernet PHYs that support MII, RGMII, and SGMII
interfaces, as shown in
10/100/1000 Mb/s and are connected to a Halo HFJ21-1G01SE Dual RJ-45 connector with
built-in magnetics (see
controls and individual 25 MHz clock crystals.
Table 2-6: Marvell Alaska PHY Configurations
PHY Interface
MII
PHY0
RGMII
(1)
PHY1 SGMII
Notes:
1. SGMII is not supported on the ML410-P. The ML410-P only supports one MII/RGMII PHY.
PLB DDR2 SDRAM Core
PLB_Clk
Device_Clk
Device_Clk_n
Device_Clk90_in
Device_Clk90_in_n
Cal_Clk
Table 2-6. The Marvell Alaska PHY devices (88E1111) operate at
Table 2-6). The PHY devices have independent MDIO and MDC
10BASE-T
x x (Full-duplex only)
x
x
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Detailed Description
DDR2 DIMM (P48)
Clock Fanout
Chip (U26)
DDR2_CLK
SSTL18_I
DDR2_CLK_N
SSTL18_I
ICS97U877
DDR2_DQ/DQS
UG085_04_113005
100BASE-T 1000BASE-T
x x (Full-duplex only)
x
-
x
37