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Revision History
The following table shows the revision history for this document.
Date
01/06/06
02/10/06
05/26/06
09/25/06
10/26/06
11/01/06
12/22/06
03/06/07
04/06/07
09/28/07
03/05/08
12/11/08
ML410 Embedded Development Platform
Downloaded from
Elcodis.com
electronic components distributor
Version
1.0
Initial Xilinx release.
1.1
Corrected pinouts in
Corrected pinouts in
1.2
Express"
section.
Updated PHY address in
1.2.1
typographical edits.
Updated
"Clock Generation," page
1.3
page 84
for RoHS-compliant revision E boards. Added
1.4
Corrected
Table 2-19, page
Added note to
1.5
Table A-1, page
1.6
Updated
Table 2-19, page 51
1.6.1
Fixed typo in
Figure 2-19, page
Corrected pinouts in
1.7
SYSACE_MPCE, and SYSACE_MPWE signals.
1.7.1
Fixed typo in
Table 2-8, page
1.7.2
Minor edits to
Revision
Table 2-20, page
53.
Table 2-5, page 33
and
Table 2-7, page 38
26,
"Serial ATA," page
51.
"RocketIO Transceivers," page
97.
and
Table A-1, page
71.
Table 2-15, page 46
for SYSACE_FPGA_CLK, SYSACE_MPD[15],
40. Updated trademark statements and copyright date.
Table A-1, page
97. Removed support for unbuffered DIMMs.
www.xilinx.com
R
Table 2-21, page
54. Expanded
and
Table 2-9, page
41. Miscellaneous
73, and
"High-Speed I/O,"
Appendix A, "Board Revisions."
17. Added board revision details to
97.
UG085 (v1.7.2) December 11, 2008
"PCI
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