Table of Contents
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Schedule of Figures
Chapter 1: Introduction to Virtex-4, ISE, and EDK
Chapter 2: ML410 Embedded Development Platform
Appendix A: Board Revisions
Appendix B: References
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Figure 2-1: ML410 High-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2-2: ML410 Board and Front Panel Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 2-3: ML410 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2-4: DDR Component Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2-5: DDR2 DIMM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2-6: PHY0 Jumper (J28) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 2-7: MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 2-8: RGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 2-9: SGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-10: FPGA UART and RS-232 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 2-11: JTAG Connections to the FPGA and System ACE CF Controller . . . . . . . . 45
Figure 2-12: PC4 JTAG Connector Pinout (J9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-13: LEDs and LCD Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 2-14: Combined Trace/Debug Connector Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2-15: CPU JTAG Header (J12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 2-16: PCI Express Power Management and Clocking. . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-17: PCI Bus and Device Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-18: ALi South Bridge Interface, M1535D+ (U15) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-19: IIC and SMBus Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 2-20: SPI EEPROM Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-21: SW3: System ACE Configuration Switch Detail . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 2-22: ATX Power Distribution and Voltage Regulation . . . . . . . . . . . . . . . . . . . . . 81
Figure 2-23: Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-24: Personality Module Connected to Embedded Development Platform. . . . 84
Figure 2-25: Edge View of Host Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 2-26: Host Board Connector Pin Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 2-27: Adapter Board Connector Pin Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-28: Z-DOK+ Utility Pins (ML410 Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-29: Z-DOK+ Utility Pins (Adapter Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure A-1: Clock Distribution for Revisions C and D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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