Xilinx ML410 User Manual page 27

R
J17
J36
X5
25 MHz
J20
J21
X7
24 MHz
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Figure 2-3 is an example of the clock distribution for the ML410 board. For clocking on
earlier revisions of the ML410 platform, see
X6
100 MHz
(OSC in Socket)
X10
Empty Socket
X8
33 MHz
OE
U53
U48
CLK100_Q0
CLK100_NQ0
100 MHz
(LVPECL)
ICS843001
ICS8740031-02
MGT_SMA_CLK_P
MGT_SMA_CLK_N
CLK_SEL0 CLK_SEL1
MGTCLK
0 0
(250 MHz)
MGTCLK
0 1
(250 MHz)
MGTCLK
1 0
(MGT SMA)
U47
MGTCLK
1 1
(MGT SMA)
300 MHz
ICS844031I-1
Figure 2-3: ML410 Clock Distribution
USER_CLKSYS
USER_CLK2
SYSACE_CLK_OSC
USER_SMA_CLK_P
USER_SMA_CLK_N
PCIE_SLOTA_CLK
PCIE_SLOTA_NCLK
CLK100_Q1
100 MHz (HCSL)
CLK100_NQ1
PCIE_SLOTB_CLK
100 MHz
(LVDS)
PCIE_SLOTB_NCLK
ICS9DB202
CLK250_Q0
CLK250_NQ0
DS90CP22
250 MHz
(LVDS)
MUX
3.3V
Q0 Q1
SW6
SGMIICLK
(250 MHz)
SGMIICLK
(MGT SMA)
SGMIICLK
(250 MHz)
SGMIICLK
ON
(MGT SMA)
(From PM Interface)
www.xilinx.com
Detailed Description
Appendix A, "Board Revisions."
FPGA (U37)
2.5V
P53
PCIe Slot A
P54
PCIe Slot B
U6
MGTCLK_P
(MGT Right Side)
Q0
MGTCLK_N
SGMIICLK_Q0
(MGT Left Side)
Q1 SGMIICLK_NQ0
CLK_SEL1
CLK_SEL0
SATACLK_Q0
(MGT Left Side)
SATACLK_NQ0
LVDS_CLKEXT_P
(MGT Right Side)
LVDS_CLKEXT_N
UG085_03_101006
27