Phy0: Mii/Rgmii - Xilinx ML410 User Manual

Chapter 2: ML410 Embedded Development Platform
38
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PHY0: MII/RGMII

PHY0 (U60) is configured at power-on or reset to the default settings shown in
PHY0 is configurable to MII, or RGMII modes through the J28 jumper settings, as shown in
Figure 2-6. These settings can be overwritten through software.
Table 2-7: PHY0 (U60) Configuration Settings for MII/RGMII
PHY Configuration
(1)
5-bit PHY address
Interrupt polarity
MDC/MDIO interface
Auto-negotiate
MDI crossover
Fibre/copper auto-select
Energy detect
MAC pause
Notes:
1. PHY address is 0b00000 for Rev. C and earlier boards.
MII to Copper
VCC2V5
J28
1
2
3
Power On Settings
0b00111
Active-Low
Enabled
Slave (operational at
10/100/1000 Mb/s)
Enabled
Disabled
Disabled
Disabled
J28
PHY_CONFIG5
PHY_CONFIG4
PHY_LED_DUPLEX
Figure 2-6: PHY0 Jumper (J28) Settings
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RGMII to Copper
VCC2V5
1
PHY_CONFIG5
2
PHY_CONFIG4
3
PHY_LED_DUPLEX
UG085_06_111505
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
R
Table 2-7.