Serial Peripheral Interface; Spi Signaling - Xilinx ML410 User Manual

Chapter 2: ML410 Embedded Development Platform

Serial Peripheral Interface

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Table 2-36 lists the IIC devices and their associated addresses.
Table 2-36: IIC Devices and Addresses
Reference
Device
Designator
LTC1694
RTC8564
24LC64
LM87
MIC2592B
DDR2_DIMM
Header
Notes:
1. The IIC bus can be controlled directly by the FPGA or indirectly by the ALi bridge over the FPGA PCI
interface.
Serial Peripheral Interface™ (SPI) is a serial interface similar to the IIC bus interface. There
are three primary differences: the SPI operates at a higher speed, there are separate
transmit and receive data lines, and the device access is chip-select based instead of
address based. EDK provides IP that integrates the SPI interface with a microprocessor
system. See the EDK Processor IP User Guide
ML410 documentation CD for more details.

SPI Signaling

There are four main signals used in the SPI interface; Clock, Data In, Data Out, and Chip
Select. Signaling rates on the SPI bus range from 1 MHz to 3 MHz, roughly a factor of 10
faster than the IIC bus interface. SPI continues to differ from IIC using active drivers for
driving the signal High and Low, while IIC only actively drives signals Low, relying on
pull-up resistors to pull the signals High.
There are four basic signals on the SPI bus:
•
Master Out Slave In (MOSI): A data line that supplies the output data from the master device
that is shifted into a slave device
•
Master In Slave Out (MISO): A data line that supplies the output data from a slave device that
is shifted into the master device
•
Serial Clock (SCK): A control line driven by the master device to regulate the flow of data and
enable a master to transmit data at a variety of baud rates
♦
The SCK line must cycle once for each data bit that is transmitted
•
Slave Select (SS): A control line dedicated to a specific slave device that allows the master
device to turn the slave device on and off
Address
SMBus accelerator that ensures data integrity with
multiple devices on the SMBus. Enhances data
U27 N/A transmission speed and reliability under all
specified SMBus loading conditions and is
compatible with the IIC bus.
IIC bus interface Real Time Clock module along
U22 0xA2 with an external rechargeable battery and charging
circuit.
U21 0xA0 64 kb electrically erasable PROM (EEPROM).
U20 0x5C Voltage/temperature monitor.
U55 0x8E Dual-slot PCI Express power controller.
0xA8
P48 DDR2
0x68
J23 N/A Front panel header connectivity for expansion.
[Ref 2]
www.xilinx.com
Description
and the data sheet available on the
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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