Xilinx Virtex-5 LXT User Manual
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Xilinx Virtex-5 LXT User Manual

Xilinx Virtex-5 LXT User Manual

Fpga prototype platform
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Virtex-5
Virtex-5 LXT/SXT/FXT
LXT/SXT/FXT
FPGA Prototype Platform
FPGA Prototype
User Guide [optional]
User Guide
UG229 (v3.0.1) May 21, 2008 [optional]
UG229 (v3.0.1) May 21, 2008
R
P/N 0402534-03

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Summary of Contents for Xilinx Virtex-5 LXT

  • Page 1 Virtex-5 Virtex-5 LXT/SXT/FXT LXT/SXT/FXT FPGA Prototype Platform FPGA Prototype User Guide [optional] User Guide UG229 (v3.0.1) May 21, 2008 [optional] UG229 (v3.0.1) May 21, 2008 P/N 0402534-03...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    Related Xilinx Documents ........
  • Page 4 Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 5: Preface: About This Guide

    ♦ Advanced SelectIO Logic Resources • Virtex-5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT and SXT platforms. • Virtex-5 FPGA RocketIO GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT platform.

  • Page 6: Additional Support Resources

    Virtex-5 LXT, SXT, and FXT platforms. • Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT platforms used for PCI Express® designs. •...

  • Page 7: Online Document

    Cross-reference link to a location Figure 2 in the Virtex-5 FPGA Red text in another document Data Sheet Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest documentation. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...
  • Page 8 Preface: About This Guide www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 9: Virtex-5 Lxt/Sxt/Fxt Fpga Prototype Platform

    The Virtex-5 FPGA prototype platform and demonstration boards enable designers to investigate and experiment with the features of Virtex-5 FPGAs. This user guide describes the features and operation of the Virtex-5 LXT/SXT/FXT prototype platform (“the board”), including how to configure chains of FPGAs and serial PROMs.

  • Page 10: Package Contents

    The Virtex-5 LXT/SXT/FXT FPGA prototype platform (the board) contains a DUT FPGA, one SPI, one BPI, and one In-System Programmable Configuration PROM (ISPROM). The ISPROM can hold up to 33,554,432 bits.

  • Page 11: Block Diagram

    MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. UG229_01_051208 Figure 1: Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Block Diagram Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 12: Related Xilinx Documents

    Prior to using the FF665, FF1136, or FF1738 prototype platform, users should be familiar with Xilinx resources. See “References” for direct links to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions: • EDK: www.xilinx.com/edk • ISE: www.xilinx.com/ise...

  • Page 13: Detailed Description

    The image might not reflect the current revision of the board. X-Ref Target - Figure 2 UG229_02_022008 Figure 2: Detailed Description of Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Components 1. Power Switch The board has an onboard power supply and an ON|OFF power switch (SW3). The green LED (DS19) lights up to indicate power from the power brick connector or the 5V jack (J32).
  • Page 14 Notes: 1. This GTP/GTX transceiver power supply name might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. 2. The maximum voltage for AVCCPLL is 1.0V for FXT devices; 1.2V for LXT and SXT devices.

  • Page 15: Power Supply Jacks

    Each bank can be powered from one of two sources (V ) by CCINT appropriate placement of jumpers on the header • VCCAUX ♦ Supplies voltage to the V DUT pins CCAUX Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 16: Configuration Ports

    The JTAG configuration port (J1) for the board allows for device programming and FPGA debug. This interface can be used with a Parallel Cable III or Parallel Cable IV cable for JTAG programming and debugging via the JTAG configuration port. www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 17: Jtag Chain

    Note: The termination jumper must be in place on the last board in the chain to connect the TDO pin of the final device to the TDO feedback chain. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 18: Upstream/Downstream Connectors

    (Figure X-Ref Target - Figure 6 VCC_TMP VCC3_EN VCC_TMP VCC3_EN VCC_TMP VCC3_EN VCC_TMP VCC3_EN VCC_TMP DOWNSTREAM_TMS DOWNSTREAM_TCK DOWNSTREAM_TDI DOWNSTREAM_TDO UG229_06_050407 Figure 6: Downstream System ACE Interface Connector (20-Pin Male) www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...
  • Page 19 7). This connector can be sourced by a downstream interface connector of another prototype platform board. X-Ref Target - Figure 7 AFX_M2 AFX_M1 AFX_M0 CS_B INIT DONE PROG CCLK RW_B DOUT_BUSY UG229_07_051506 Figure 7: Upstream Interface Connector (44-Pin Female) Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 20: Prototyping Area

    An onboard battery holder (B1) is connected to the VBATT pin of the DUT. If an external power supply is used, the associated jumper must be removed; instead, use a 12-mm lithium coin battery (3V). www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 21: Oscillator Sockets

    Table 7: SMA Clock Pin Connections Pin Number Label Clock Name FF665 FF1136 FF1738 IO_L0P_CC_GC_3 IO_L0N_CC_GC_3 IO_L9P_GC_3 IO_L9N_GC_3 IO_L9P_CC_GC_4 AB15 AH18 AP16 IO_L9N_CC_GC_4 AC16 AG17 AP15 IO_L6P_GC_4 AC18 AG18 AM27 IO_L6N_GC_4 AB17 AF19 AM26 Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 22: Dut Socket

    IO _L7N _GC _3 IO_L8P_GC_3 IO_L8N_GC_3 IO_L4P_GC_4 AB19 AG21 AP27 IO_L4N_GC_VREF_4 AC19 AG20 AN28 IO_L5P_GC_4 AC12 AH15 AM16 IO_L5N_GC_4 AC13 AG15 AM17 IO_L7P_GC_VRN_4 AB14 AH17 AN15 IO_L7N_GC_VRP_4 AC14 AG16 AN16 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 23: User Leds (Active-High)

    D0-D7 and D24-D31 (corresponding to LED 0- LED 15). Table 9 shows the LED assignments. Table 9: LED Assignments and Corresponding I/O Pin Number For Package Type After Configuration FF665 FF1136 FF1738 Available as user LEDs Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 24: Program Switch

    Sets the ISPROM for serial or select map configuration. Selects one of two modes of CCLK operation: • ISPROM provides CCLK (PROM CLKOUT) • FPGA provides CCLK (FPGA CCLK) www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 25: Spi Interface

    AF14 AM13 The J2 connector allows users to connect a Parallel Cable IV ribbon cable to configure the SPI device. For SPI programming, refer to the latest version of Xilinx iMPACT software tool documentation [Ref 6]. To set the Mode pins for SPI configuration, see the Virtex-5 FPGA...

  • Page 26: Bpi Interface

    AB12 AH13 AL16 AC11 AH14 AL15 DQ10 AB20 AH19 AP28 DQ11 AB21 AH20 AN29 DQ12 AB11 AG13 AL17 DQ13 AB10 AH12 AK17 DQ14 AA20 AH22 AP30 DQ15 AG22 AN30 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...
  • Page 27 IOBs. Jumper pins 3 to 5 and pins 4 to 6 connect RS0 and RS1 to the highest address lines of the BPI device. See the Virtex-5 FPGA Configuration User Guide [Ref 3] for more information on how the RS signals can be applied in a user’s application. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 28: Gtp/Gtx Transceiver Clocks To Sma

    REFCLKN_116 REFCLKP_116 REFCLKN_118 REFCLKP_118 Notes: 1. These GTP/GTX clock pin names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

  • Page 29: Configuration Mode Pins

    Master BPI-Down Output Master SelectMAP Output JTAG Input (TCK) Slave SelectMAP Input Slave Serial Input X-Ref Target - Figure 9 (HDR_2x29) UG229_09_041108 Figure 9: Default Configuration Mode Jumper Settings Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008...

  • Page 30: References

    UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs. UG193, XtremeDSP Design Considerations. UG191, Virtex-5 FPGA Configuration User Guide. 10. UG192, Virtex-5 FPGA System Monitor User Guide. 11. UG195, Virtex-5 FPGA Packaging and Pinout Specification. www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 (v3.0.1) May 21, 2008...

This manual is also suitable for:

Virtex-5 sxtVirtex-5 fxt

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