Xilinx ML410 User Manual page 30

Chapter 2: ML410 Embedded Development Platform
30
Downloaded from Elcodis.com electronic components distributor
Table 2-4 lists the connections from the FPGA to the DDR interface. Note that the
DDR1_DQ signal names do not correlate as the FPGA uses IBM notation, big endian, while
the DDR components use Intel notation, little endian.
Table 2-4: Connections from FPGA to DDR1 SDRAMs (U42 and U43)
XC4FX60 Pin
UCF Signal Name
DDR1_WE_N
DDR1_RAS_N
DDR1_CAS_N
DDR1_DQS[0]
DDR1_DQS[1]
DDR1_DQS[2]
DDR1_DQS[3]
DDR1_DM[0]
DDR1_DM[1]
DDR1_DM[2]
DDR1_DM[3]
DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[4]
DDR1_DQ[5]
DDR1_DQ[6]
DDR1_DQ[7]
DDR1_DQ[8]
DDR1_DQ[9]
DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[12]
DDR1_DQ[13]
DDR1_DQ[14]
DDR1_DQ[15]
DDR1_DQ[16]
DDR1_DQ[17]
www.xilinx.com
Schematic Signal
(U37) Name
E27 DDR1_WE_N
D27 DDR1_RAS_N
D26 DDR1_CAS_N
F20 DDR1_DQS[0]
G20 DDR1_DQS[1]
G25 DDR1_DQS[2]
F25 DDR1_DQS[3]
F21 DDR1_DM[0]
G22 DDR1_DM[1]
E23 DDR1_DM[2]
G23 DDR1_DM[3]
E17 DDR1_D[0]
E18 DDR1_D[1]
F18 DDR1_D[2]
G18 DDR1_D[3]
F19 DDR1_D[4]
E19 DDR1_D[5]
D21 DDR1_D[6]
E21 DDR1_D[7]
G21 DDR1_D[8]
H20 DDR1_D[9]
J20 DDR1_D[10]
J21 DDR1_D[11]
K21 DDR1_D[12]
L21 DDR1_D[13]
J22 DDR1_D[14]
H22 DDR1_D[15]
C22 DDR1_D[16]
C23 DDR1_D[17]
ML410 Embedded Development Platform
DDR1 DDR1
SDRAM SDRAM
(U42) (U43)
21 21
23 23
22 22
16 -
51 -
- 16
- 51
20 -
47 -
- 20
- 47
2 -
4 -
5 -
7 -
8 -
10 -
11 -
13 -
54 -
56 -
57 -
59 -
60 -
62 -
63 -
65 -
- 2
- 4
UG085 (v1.7.2) December 11, 2008
R