Xilinx ML410 User Manual page 31

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Table 2-4: Connections from FPGA to DDR1 SDRAMs (U42 and U43) (Cont'd)
XC4FX60 Pin
UCF Signal Name
DDR1_DQ[18]
DDR1_DQ[19]
DDR1_DQ[20]
DDR1_DQ[21]
DDR1_DQ[22]
DDR1_DQ[23]
DDR1_DQ[24]
DDR1_DQ[25]
DDR1_DQ[26]
DDR1_DQ[27]
DDR1_DQ[28]
DDR1_DQ[29]
DDR1_DQ[30]
DDR1_DQ[31]
DDR1_CS_N
DDR1_CKE
DDR1_LOOP
DDR1_LOOP
DDR1_CK1_P
DDR1_CK1_N
DDR1_CLK_FB
DDR1_BA[0]
DDR1_BA[1]
DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
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Schematic Signal
(U37) Name
C24 DDR1_D[18]
C25 DDR1_D[19]
D22 DDR1_D[20]
D24 DDR1_D[21]
D25 DDR1_D[22]
C28 DDR1_D[23]
F23 DDR1_D[24]
F24 DDR1_D[25]
F26 DDR1_D[26]
G26 DDR1_D[27]
H25 DDR1_D[28]
H24 DDR1_D[29]
E24 DDR1_D[30]
E22 DDR1_D[31]
C27 DDR1_CS_N
H14 DDR1_CKE
E26 -
G17 -
F28 DDR1_CK1_P
E28 DDR1_CK1_N
K18 DDR1_CLK_FB
J25 DDR1_BA[0]
J26 DDR1_BA[1]
P24 DDR1_A[0]
P22 DDR1_A[1]
N22 DDR1_A[2]
N23 DDR1_A[3]
N24 DDR1_A[4]
M23 DDR1_A[5]
L24 DDR1_A[6]
L25 DDR1_A[7]
L26 DDR1_A[8]
Detailed Description
DDR1 DDR1
SDRAM SDRAM
(U42) (U43)
- 5
- 7
- 8
- 10
- 11
- 13
- 54
- 56
- 57
- 59
- 60
- 62
- 63
- 65
24 24
44 44
- -
- -
45 45
46 46
- -
26 26
27 27
29 29
30 30
31 31
32 32
35 35
36 36
37 37
38 38
39 39
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