Xilinx ML410 User Manual page 28

Chapter 2: ML410 Embedded Development Platform
28
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Table 2-3 shows the ML410 clock connections.
Table 2-3: Clock Connections
Schematic Net Name
USER_CLKSYS
USER_CLK2
USER_SMA_CLK_N
USER_SMA_CLK_P
PM_CLK_TOP
PM_CLK_BOT
LVDS_CLKEXT_P
LVDS_CLKEXT_N
SGMIICLK_Q0 (Selectable)
SGMIICLK_NQ0 (Selectable)
MGTCLK_P_110 (Selectable)
MGTCLK_N_110 (Selectable)
SATACLK_Q0 (Selectable)
SATACLK_NQ0 (Selectable)
Notes:
1. See "High-Speed I/O," page
2. These clocks are differential pairs through the RocketIO transceivers and are not available on ML410-P
boards. See Figure 2-3, page
www.xilinx.com
Clock
FPGA Pin (U37)
Source
X6 J16
X10 L15
J36 AG18
J17 AF18
PM1.F9 K16
PM2.F10 AD21
PM1.F12 J1
PM1.F11 K1
M34
N34
AP3
AP4
AP29
AP28
84.
27.
ML410 Embedded Development Platform
Description
100 MHz socketed user clock
oscillator (2.5V).
Socket for user-supplied clock
(1)
oscillator (3.3V) .
Ω differential SMA
100
connections that can be used as a
differential pair clock.
Ω differential SMA
100
connections that can be used as a
differential pair clock. J17 can be
Ω .
used single ended at 50
Personality module clock (top)
(1)
(2.5V) .
Personality module clock
(1)
(bottom) (2.5V) .
(1) (2)
LVDS pair (2.5V) .
Frequency is user-defined.
(1) (2)
LVDS pair (2.5V) .
Frequency is user-defined.
SMA or onboard 250 MHz clock
source selectable through
(2)
SW6 .
SMA or onboard 250 MHz clock
source selectable through
(2)
SW6 .
SMA or onboard 250 MHz clock
source selectable through
(2)
SW6 .
SMA or onboard 250 MHz clock
source selectable through
(2)
SW6 .
(2)
300 MHz Serial ATA clock
(2)
300 MHz Serial ATA clock
UG085 (v1.7.2) December 11, 2008
R
.
.