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R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from
Elcodis.com
electronic components distributor
Figure 2-7
and
Figure 2-8
show the MII and RMII interfaces. Functional differences are
shown in bold text to indicate the behavior of the signals on each interface.
FPGA
FPGA
www.xilinx.com
PHY (U60)
PHY_TXCLK
PHY_TXER
PHY_TXCTL_TXEN
PHY_TXD[3:0]
PHY_RXCLK
PHY_RXER
PHY_RXCTL_RXDV
PHY_RXD[3:0]
PHY_RESET
PHY_INT
PHY_MDC
PHY_MDIO
Figure 2-7: MII Interface
PHY (U60)
PHY_GTXCLK
PHY_TXCTL_TXEN
PHY_TXD[3:0]
PHY_RXCLK
PHY_RXCTL_RXDV
PHY_RXD[3:0]
PHY_RESET
PHY_INT
PHY_MDC
PHY_MDIO
Figure 2-8: RGMII Interface
Detailed Description
UG085_07_111505
UG085_08_111805
39
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