Xilinx ML410 User Manual page 98

J17
J36
X5
25 MHz
J20
J21
X7
25 MHz
98
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The MGT and SATA clock generation and distribution for earlier board revisions
(Figure A-1) differs from revision E
X6
100 MHz
(OSC in Socket)
X10
Empty Socket
X8
33 MHz
OE
U48
CLK100_Q0
CLK100_NQ0
100 MHz
ICS843001
MGT_SMA_CLK_P
ICS874003
MGT_SMA_CLK_N
CLK_SEL0 CLK_SEL1
MGTCLK
0 0
(125 MHz)
MGTCLK
0 1
(125 MHz)
MGTCLK
1 0
(MGT SMA)
U47
MGTCLK
1 1
(MGT SMA)
150 MHz
ICS844001-1
Figure A-1: Clock Distribution for Revisions C and D
(Figure 2-3, page
USER_CLKSYS
USER_CLK2
SYSACE_CLK_OSC
USER_SMA_CLK_P
USER_SMA_CLK_N
U53
PCIE_SLOTA_CLK
PCIE_SLOTA_NCLK
100 MHz
PCIE_SLOTB_CLK
PCIE_SLOTB_NCLK
CLK125_Q0
CLK125_NQ0
DS90CP22
125 MHz
MUX
3.3V
Q0 Q1
SW6
SGMIICLK
(125 MHz)
SGMIICLK
(MGT SMA)
SGMIICLK
(125 MHz)
SGMIICLK
ON
(MGT SMA)
(From PM Interface)
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27).
FPGA (U37)
2.5V
P53
PCIe Slot A
P54
PCIe Slot B
U6
MGTCLK_P
(MGT Right Side)
Q0
MGTCLK_N
SGMIICLK_Q0
SGMIICLK_NQ0 (MGT Left Side)
Q1
CLK_SEL1
CLK_SEL0
SATACLK_Q0
SATACLK_NQ0 (MGT Left Side)
LVDS_CLKEXT_P
(MGT Right Side)
LVDS_CLKEXT_N
UG085_APDX_A_01_101006
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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