Gpio Led Interface; Gpio Lcd Interface - Xilinx ML410 User Manual

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor

GPIO LED Interface

All LEDs connected to the GPIO lines illuminate green when driven with a logic 0 and
extinguish with a logic 1.
FPGA to the non-inverting buffer (U36).
Table 2-16: GPIO LED Connection from FPGA to U36
UCF Signal
FPGA Pin (U37)
Name
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7

GPIO LCD Interface

The GPIO LCD interface has eight input/output signals used as data and three output-
only signals used as control. The data signals are controlled by the logic level of the
FPGA_LCD_DIR signal. A logic 1 on FPGA_LCD_DIR configures the LVCC3245 to drive
the J13 header, while a logic 0 on FPGA_LCD_DIR configures the LVCC3245 to drive the
FPGA.
Table 2-17 shows the data bus signals on the GPIO LCD interface from the FPGA to U35.
Table 2-17: GPIO LCD Data Signals from FPGA to U35
UCF Signal Name
FPGA_LCD_DB0
FPGA_LCD_DB1
FPGA_LCD_DB2
FPGA_LCD_DB3
FPGA_LCD_DB4
FPGA_LCD_DB5
FPGA_LCD_DB6
FPGA_LCD_DB7
FPGA_LCD_DIR
The control signals allow the user to read/write the LCD character display in conjunction
with the eight LCD data signals defined in
data sheet located on the ML410 documentation CD for more information.
Table 2-16 shows the connections for the GPIO LEDs from the
Schematic
Signal Name
AF19 DBG_LED_0
AD5 DBG_LED_1
AD6 DBG_LED_2
AD7 DBG_LED_3
AB8 DBG_LED_4
AC7 DBG_LED_5
AC9 DBG_LED_6
AC10 DBG_LED_7
Schematic Signal
FPGA Pin (U37)
Name
AJ21 FPGA_LCD_DB0
AG21 FPGA_LCD_DB1
AJ20 FPGA_LCD_DB2
AH20 FPGA_LCD_DB3
AG20 FPGA_LCD_DB4
AK19 FPGA_LCD_DB5
AJ19 FPGA_LCD_DB6
AH19 FPGA_LCD_DB7
AK18 FPGA_LCD_DIR
Table 2-17. See the AND491GST LCD display
www.xilinx.com
Detailed Description
LVC244
LED
Buffer (U36)
2 DS20
4 DS19
6 DS18
8 DS17
11 DS16
13 DS15
15 DS14
17 DS13
LVCC3245
LCD I/F
Translator
(J13)
(U35)
3
4
5
6
7
8
9
10
2
7
8
9
10
11
12
13
14
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