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R
PCI Bus
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Table 2-23: Connections from FPGA to PCI Express Slot B
Net Name
RXPPADA_101
RXNPADA_101
RXPPADB_101
RXNPADB_101
TXPPADA_101
TXNPADA_101
TXPPADB_101
TXNPADB_101
RXPPADA_102
RXNPADA_102
RXPPADB_114
RXNPADB_114
TXPPADA_102
TXNPADA_102
TXPPADB_114
TXNPADB_114
PCIE_SLOTB_PRSNT2#
PCIE_SLOTB_PWRGD#
PCIE_SLOTB_WAKE#
ML410 platforms provide the FPGA with access to two 33 MHz/32-bit PCI buses, a
primary 3.3V PCI bus and a secondary 5V PCI bus. The FPGA is directly connected to the
primary 3.3V PCI bus while the 5V PCI bus is connected to the primary PCI bus via a
PCI-to-PCI bridge. Several PCI devices are available on the PCI buses as well as four PCI
add-in card slots. All PCI bus signals driven by the FPGA comply with the I/O
requirements specified in the PCI Local Bus Specification, Revision 2.2 (see www.pcisig.com).
The majority of the ML410 features are accessed over the 33 MHz/32-bit PCI bus. The
Virtex-4 PPC405 processors can access the primary PCI bus through the EDK PCI Host
Bridge IP. All PCI configuration and control can be performed via a PCI Host Bridge
implemented in the FPGA fabric. The primary PCI bus is wired so that the FPGA fabric
must be used to provide PCI bus arbitration logic. EDK also provides PCI Arbiter IP. See
the EDK Processor IP User Guide
in this section.
The FPGA is responsible generating the PCI RST signal as well as the PCI CLK signal. The
FPGA fabric is used to generate several PCI clocks that drive each of the PCI devices/slots
shown in
Figure
2-17. All six PCI clock outputs are length matched. Because the FPGA
www.xilinx.com
FPGA Pin (U37)
Connector Pin (P54)
A20
A21
A28
A29
A23
A24
A25
A26
A31
A32
A10
A9
D34
E34
A13
A12
F16
G13
F14
[Ref 2]
for more information about the EDK IP mentioned
Detailed Description
25
26
21
22
105
106
101
102
16
17
29
30
96
97
109
110
130
11
93
57
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