Xilinx ML410 User Manual page 40

Chapter 2: ML410 Embedded Development Platform
40
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Table 2-8 shows the MII/RGMII interface for PHY0.
Table 2-8: PHY0 MII/RGMII Interface
Signal Name
PHY_TXCLK
PHY_RXC_RXCLK
PHY_GTXCLK
PHY_TXD3
PHY_TXD2
PHY_TXD1
PHY_TXD0
PHY_TXER
(1)
PHY_TXCTL_TXEN
PHY_RXD3
PHY_RXD2
PHY_RXD1
PHY_RXD0
PHY_RXER
(2)
PHY_RXCTL_RXDV
PHY_INT
PHY_RESET
PHY_MDIO
PHY_MDC
Notes:
1. PHY_TXCTL_TXEN is a dual-purpose pin. In MII mode, it is TXEN. In RGMII mode, it is TXCTL.
2. PHY_RXCTL_RXDV is a dual-purpose pin. In MII mode, it is RXDV. In RGMII mode, it is RXCTL.
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FPGA Pin
MII
(U37)
J14 x
K19 x
J19
K9 x
K11 x
K12 x
K13 x
L14 x
L11 x
J9 x
J10 x
J11 x
J12 x
H18 x
H12 x
M11 x
M12 x
L13 x
M13 x
ML410 Embedded Development Platform
RGMII Description
MII transmit clock
x Receive clock
x RGMII transmit clock
x
x
Transmit data bits
x
x
Transmit controls
x
x
x
Receive data bits
x
x
Receive control signals
x
x PHY0 interrupt
x PHY0 reset
PHY0 management data
x
input/output
PHY0 management data
x
clock
UG085 (v1.7.2) December 11, 2008
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