Front Panel Interface (J23) - Xilinx ML410 User Manual

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Table 2-40 shows the output combinations of the clock multiplexer.
Table 2-40: Outputs of the Clock Multiplexer (U6)
CLK_SEL0 CLK_SEL1
0 0
0 1
1 0
1 1

Front Panel Interface (J23)

The front panel interface connector (J23) is a 24-pin header that accepts a standard IDC 24
pin connector (0.1 inch pitch). J23 provides an optional means to control and gather status
information from the ML410 if enclosed in a case similar to a desktop computer. The
functionality listed below can easily be connected with a custom user-provided cable that
connects to user logic designed to control and monitor the functionality available through
the front panel interface.
The front panel interface provides the following control capability:
♦
Power ON|OFF the board
- ML410 platforms are delivered with a jumper installed on J23
♦
Eight System ACE configuration selections
- Connects to the three System ACE configuration address lines
♦
System ACE Reset
- Active-Low input (pulsed)
♦
CPU Reset
Active-Low input (pulsed)
-
The front panel interface provides access to the following status information:
♦
FPGA configuration DONE output
♦
IDE disk access output
♦
ATX power output
♦
Two FPGA user-defined output signals
♦
ATX speaker output
♦
Keyboard inhibit input (active-Low)
Note: All front panel interface outputs, except for the speaker out, can drive LEDs.
Q0
250 MHz MGTCLK sourced
from X5
250 MHz MGTCLK sourced
from X5
MGTCLK sourced from the
MGT SMA connectors at J20
and J21
MGTCLK sourced from the
MGT SMA connectors at J20
and J21
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Detailed Description
Q1
250 MHz SGMIICLK sourced
from X5
SGMIICLK sourced from the
MGT SMA connectors at J20
and J21
250 MHz SGMIICLK sourced
from X5
SGMIICLK sourced from the
MGT SMA connectors at J20
and J21
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