Pm2 User I/O - Xilinx ML410 User Manual

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Table 2-48: PM1 Pinout (Cont'd)
FPGA
PM1 Pin
Pin (U37)
D19 AP15
D20 AP14
F1 AB13
F2 AA13
F3 Y3
F4 Y4
F5 W6
F6 W7
F7 V7
F8 V8
F9 K16
F10 NC
F11 K1
F12 J1
F13 A3
F14 A4
F15 AG1
F16 AF1
F17 N1
F18 M1
F19 AP7
F20 AP6
Table 2-49: PM2 Pinout
FPGA
PM2 Pin
Pin (U37)
A1 AJ10
A2 AH10
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Pin Description
RXNPADB_109
RXPPADB_109
IO_L3P_8
IO_L3N_8
IO_L6N_12
IO_L6P_12
IO_L4N _VREF _12
IO_L4P_12
IO_L2N_12
IO_L2P_12
IO_L2P_GC_VRN_LC_3
NC
MGTCLK_N_113
MGTCLK_P_113
TXNPADA_113
TXPPADA_113
TXNPADA_110
TXPPADA_110
RXNPADA_112
RXPPADA_112
RXNPADA_109
RXPPADA_109

PM2 User I/O

The PM2 connector makes most of the LVDS pairs available to the user, along with single-
ended signals. Table 2-49
Pin Description
IO_L18N_8
IO_L18P_8
ML410 Schematic FPGA Bank
Net V
CCO
RXNPADB_109
RXPPADB_109
PM_IO_88 2.5V
PM_IO_89 2.5V
PM_IO_3V_10 3V
PM_IO_3V_4 3V
PM_IO_3V_15 3V
PM_IO_3V_0 3V
PM_IO_3V_23 3V
PM_IO_3V_11 3V
PM_CLK_TOP 2.5V
NC NC
LVDS_CLKEXT_
2.5V
N
LVDS_CLKEXT_
2.5V
P
TXNPADA_113
TXPPADA_113
TXNPADA_110
TXPPADA_110
RXNPADA_112
RXPPADA_112
RXNPADA_109
RXPPADA_109
shows the pinout for the PM2 connector on the ML410.
ML410 FPGA Bank
Schematic Net VCCO
PM_IO_63 2.5V
PM_IO_62 2.5V
www.xilinx.com
High-Speed I/O
Pin Function
MGT RX pair received by host
FPGA
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Single-ended 50Ω impedance
Clock
No Connect
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
MGT TX pair driven by host
FPGA
MGT TX pair driven by host
FPGA
MGT RX pair received by host
FPGA
MGT RX pair received by host
FPGA
Pin Function
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
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