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Xilinx ML410 User Manual

Xilinx ML410 User Manual

Embedded development platform
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ML410 Embedded
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User Guide
UG085 (v1.7.2) December 11, 2008
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Summary of Contents for Xilinx ML410

  • Page 1 ML410 Embedded Development Platform User Guide UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    Platform Studio Features ..........19 Chapter 2: ML410 Embedded Development Platform Overview .
  • Page 4 ......... . . 70 IIC/SMBus on ML410 Platforms Serial Peripheral Interface .
  • Page 5 Appendix A: Board Revisions Appendix B: References ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 6 ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 7: Schedule Of Figures

    Figure 2-28: Z-DOK+ Utility Pins (ML410 Side) ........
  • Page 8 ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 9: Schedule Of Tables

    Table 1-1: Virtex-4 FX Family Members ......... . 16 Chapter 2: ML410 Embedded Development Platform Table 2-1: I/O Voltage Rail of FPGA Banks.
  • Page 10 Table A-2: MGT and SATA Clock Connections for Revisions C and D ....99 Appendix B: References www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 11: Preface: About This Guide

    Preface About This Guide This manual accompanies the ML410 series of Embedded Development Platforms and contains information about the ML410 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “Introduction to Virtex-4, ISE, and EDK,”...

  • Page 12: Online Document

    “Additional Resources” for details. Cross-reference link to a location Blue text in the current document Refer to “Title Formats” in Chapter 1 for details. www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 13 Red text in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 14 Preface: About This Guide www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 15: Chapter 1: Introduction To Virtex-4, Ise, And Edk

    Summary of Virtex-4 FX Features The Virtex-4 family has an impressive collection of both programmable logic and hard IP, historically the domain of ASICs. The Virtex-4 FX FPGAs used on ML410 platforms are high-performance, full-featured solutions for embedded platform applications.

  • Page 16: Powerpc™ 405 Core

    Optimized FPGA-based coprocessor connection ♦ Automatic decode of PowerPC floating-point instructions ♦ Allows custom instructions (decode for up to eight instructions) ♦ Extremely efficient microcontroller-style interfacing www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 17: Rocketio Transceivers

    PACE, designers are able to observe and describe information regarding the connectivity and resource requirements of a design, resource layout of a target FPGA, and the mapping of the design onto the FPGA via location/area. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 18: Synthesis

    Xilinx understands the critical issues such as complex board layout, signal integrity, high- speed bus interface, high-performance I/O bandwidth, and electromagnetic interference for system-level designers. To ease the system level designers' challenge, ISE provides support to all Xilinx leading FPGA technologies: •...

  • Page 19: Embedded Development Kit

    Sample projects Platform Studio Features The Xilinx Platform Studio (XPS) is a graphical user interface technology that integrates all of the processes from design entry to design debug and verification. XPS streamlines development with the embedded features of the Xilinx Virtex-4 FX family of devices, featuring the industry's only immersed dual PowerPC processors and innovative Auxiliary Processor Unit (APU) controller for accelerating processing functions.
  • Page 20 Chapter 1: Introduction to Virtex-4, ISE, and EDK www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 21: Chapter 2: Ml410 Embedded Development Platform

    30,000 logic cells, over 2,400 kb of block RAM, dual IBM PowerPC 405 (PPC405) processors, and RocketIO transceivers available in the FPGA, the ML410 provides an onboard Ethernet MAC PHY, DDR memory, multiple PCI bus slots, and standard front panel interface ports within an ATX form factor motherboard.
  • Page 22 3.5mm headphone and microphone connectors Two USB peripheral ports and one parallel port General purpose I/O (GPIO) Flash memory interface • Two serial ATA connectors • Xilinx Personality Module (XPM) interface for access to: ♦ RocketIO transceivers ♦ SPI4.2 ♦ GPIO ♦...

  • Page 23: Block Diagram

    Slots UG085_02_120905 Figure 2-1: ML410 High-Level Block Diagram Related Xilinx Documents Prior to using the ML410 Embedded Development Platform, users should be familiar with Xilinx resources. See Appendix B, “References” for direct links to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions: •...

  • Page 24: Detailed Description

    Chapter 2: ML410 Embedded Development Platform Detailed Description The ML410, shown in Figure 2-2, is an example of the ML410 series described in this user guide. ALi GPIO Prog Pushbutton, SW4 Header, J5 System ACE Status and Error LEDs Parallel Cable IV...

  • Page 25: Configuration

    DDR2 DIMM interface. See the Virtex-4 Data Sheet [Ref 3] for more information regarding I/O standards. The voltage applied to the FPGA I/O banks used by the ML410 platforms is summarized Table 2-1. Table 2-1: I/O Voltage Rail of FPGA Banks...

  • Page 26: Clock Generation

    Yes, 49.9 Clock Generation ML410 boards are equipped with two crystal oscillator sockets (X6 and X10) each wired for standard LVTTL-type oscillators. Both sockets accept half- and full-size oscillators. See the reference design documentation on the ML410 website for examples of how to set up the clocks on ML410 boards.
  • Page 27 Detailed Description Figure 2-3 is an example of the clock distribution for the ML410 board. For clocking on earlier revisions of the ML410 platform, see Appendix A, “Board Revisions.” 100 MHz (OSC in Socket) FPGA (U37) USER_CLKSYS USER_CLK2 Empty Socket 2.5V...
  • Page 28 AP28 300 MHz Serial ATA clock Notes: 1. See “High-Speed I/O,” page 2. These clocks are differential pairs through the RocketIO transceivers and are not available on ML410-P boards. See Figure 2-3, page www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 29: Ddr And Ddr2 Memory

    Detailed Description DDR and DDR2 Memory ML410 platforms have two types of double data rate (DDR) memory, two component DDRs and a DDR2 SDRAM DIMM. The two memory systems are independent and enable users to build independent systems. DDR Component Memory The board contains 64 MB of DDR SDRAM (U42 and U43).
  • Page 30 Chapter 2: ML410 Embedded Development Platform Table 2-4 lists the connections from the FPGA to the DDR interface. Note that the DDR1_DQ signal names do not correlate as the FPGA uses IBM notation, big endian, while the DDR components use Intel notation, little endian.
  • Page 31 DDR1_CLK_FB DDR1_CLK_FB DDR1_BA[0] DDR1_BA[0] DDR1_BA[1] DDR1_BA[1] DDR1_A[0] DDR1_A[0] DDR1_A[1] DDR1_A[1] DDR1_A[2] DDR1_A[2] DDR1_A[3] DDR1_A[3] DDR1_A[4] DDR1_A[4] DDR1_A[5] DDR1_A[5] DDR1_A[6] DDR1_A[6] DDR1_A[7] DDR1_A[7] DDR1_A[8] DDR1_A[8] ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 32: Ddr2 Sdram Dimm

    The DDR2 DIMM is a standard 240-pin DIMM socket, supporting standard computer DDR2 memory. ML410 platforms are shipped with a single-rank registered 256 MB PC2-3200 DDR2-400 Dual Inline Memory Module (DIMM). The DDR2 DIMM is commercially available from Wintec Industries as part number WID32M72R8 (-5 speed grade). The DDR2 DIMM uses nine 32M x 8 DDR2 SDRAM devices with 14-row address lines, 10-column address lines, and two bank address lines.
  • Page 33 DDR2_DQS[6] AG32 DDR2_DQS[06] DDR2_DQSn[7] AE31 DDR2_DQSn[07] DDR2_DQS[7] AE32 DDR2_DQS[07] DDR2_A[0] DDR2_A[00] DDR2_A[1] DDR2_A[01] DDR2_A[2] DDR2_A[02] DDR2_A[3] DDR2_A[03] DDR2_A[4] DDR2_A[04] DDR2_A[5] DDR2_A[05] DDR2_A[6] AD26 DDR2_A[06] ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 34 Chapter 2: ML410 Embedded Development Platform Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont’d) XC4FX60 Pin Schematic Signal DDR2 DIMM UCF Signal Name (U37) Name (P48) DDR2_A[7] AC25 DDR2_A[07] DDR2_A[8] DDR2_A[08] DDR2_A[9] DDR2_A[09] DDR2_A[10] DDR2_A[10] DDR2_A[11] DDR2_A[11]...
  • Page 35 DDR2_DQ[33] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[34] DDR2_DQ[35] DDR2_DQ[35] DDR2_DQ[36] DDR2_DQ[36] DDR2_DQ[37] AB32 DDR2_DQ[37] DDR2_DQ[38] AC32 DDR2_DQ[38] DDR2_DQ[39] AD32 DDR2_DQ[39] DDR2_DQ[40] AB27 DDR2_DQ[40] DDR2_DQ[41] DDR2_DQ[41] DDR2_DQ[42] DDR2_DQ[42] ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 36 Chapter 2: ML410 Embedded Development Platform Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont’d) XC4FX60 Pin Schematic Signal DDR2 DIMM UCF Signal Name (U37) Name (P48) DDR2_DQ[43] DDR2_DQ[43] DDR2_DQ[44] AA31 DDR2_DQ[44] DDR2_DQ[45] AB31 DDR2_DQ[45] DDR2_DQ[46] AD31 DDR2_DQ[46]...

  • Page 37: Tri-Mode (10/100/1000 Mb/S) Ethernet Phy

    (Full-duplex only) PHY0 RGMII x (Full-duplex only) PHY1 SGMII Notes: 1. SGMII is not supported on the ML410-P. The ML410-P only supports one MII/RGMII PHY. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 38: Phy0: Mii/Rgmii

    Chapter 2: ML410 Embedded Development Platform PHY0: MII/RGMII PHY0 (U60) is configured at power-on or reset to the default settings shown in Table 2-7. PHY0 is configurable to MII, or RGMII modes through the J28 jumper settings, as shown in Figure 2-6.
  • Page 39 PHY_MDIO UG085_07_111505 Figure 2-7: MII Interface FPGA PHY (U60) PHY_GTXCLK PHY_TXCTL_TXEN PHY_TXD[3:0] PHY_RXCLK PHY_RXCTL_RXDV PHY_RXD[3:0] PHY_RESET PHY_INT PHY_MDC PHY_MDIO UG085_08_111805 Figure 2-8: RGMII Interface ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 40 Chapter 2: ML410 Embedded Development Platform Table 2-8 shows the MII/RGMII interface for PHY0. Table 2-8: PHY0 MII/RGMII Interface FPGA Pin Signal Name RGMII Description (U37) PHY_TXCLK MII transmit clock PHY_RXC_RXCLK Receive clock PHY_GTXCLK RGMII transmit clock PHY_TXD3 PHY_TXD2 Transmit data bits...

  • Page 41: Phy1: Sgmii

    MDIO interface for PHY1. Table 2-11: PHY1 MDIO Interface FPGA Pin Signal Name Description (U37) PHY1_MDIO AE19 PHY1 management data input/output PHY1_MDC AD19 PHY1 management data clock ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 42 Chapter 2: ML410 Embedded Development Platform SGMII Interface FPGA PHY (U61) PHY1_TXD_P PHY1_TXD_N PHY1_RXD_P PHY1_RXD_N PHY1_MDC PHY1_MDIO UG085_09_111505 Figure 2-9: SGMII Interface www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 43: Rs-232 Ports

    RS-232 connections to the FPGA for UART0 and UART1. Table 2-12: FPGA RS-232 Connections for UART0 Signal Name FPGA Pin (U37) UART0_CTS_N UART0_RTS_N UART0_RXD UART0_TXD ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 44: System Ace Cf Controller

    Introduction to the System ACE Configuration Solution The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port.

  • Page 45: Board Bring-Up Through The Jtag Interface

    (From J12) CPU_TDO 2.5V 2.5V JTAG_SRC_SEL Schematic Sheet 10 Schematic Sheet 33 UG085_11_120805 Figure 2-11: JTAG Connections to the FPGA and System ACE CF Controller ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 46: Non-Volatile Storage Through The Mpu Interface

    Chapter 2: ML410 Embedded Development Platform The pinout shown in Figure 2-12 is compatible with the Parallel Cable IV (PC4) JTAG programming solution. The J9 header is used when programming the FPGA by way of the PC4 download cable. INIT...

  • Page 47: Gpio Leds And Lcd

    SYSACE_MPIRQ GPIO LEDs and LCD ML410 platforms provide direct GPIO access to eight LEDs for general purpose use, and provide indirect access to a 16-pin connector (J13) that interfaces the FPGA to a 2-line by 16-character LCD display, AND491GST. A simple register interface handles access to the FPGA’s GPIO signals.
  • Page 48 Chapter 2: ML410 Embedded Development Platform Figure 2-13 shows the connectivity of the ML410 LEDs and LCD. VCC3V3 Non-Inverting Buffer (U36) VCCA DBG_LED_0 DBG_LED_1 DBG_LED_2 DBG_LED_3 Output to Green LEDs DBG_LED_4 DBG_LED_5 DBG_LED_6 DBG_LED_7 SN74LVC244A VCC3V3 Non-Inverting Buffer (U33) VCCA...

  • Page 49: Gpio Led Interface

    The control signals allow the user to read/write the LCD character display in conjunction with the eight LCD data signals defined in Table 2-17. See the AND491GST LCD display data sheet located on the ML410 documentation CD for more information. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 50: Cpu Debugging Interfaces

    JTAG/TRACE (P8) mictor connector and the CPU JTAG header (J12). These connectors can be used in conjunction with third party tools, or in some cases with the Xilinx Parallel Cable IV, to debug software as it runs on the processor. The P8 mictor connector supports the Agilent ATC2 core that can be mapped using the ChipScope Pro CORE Generator™...
  • Page 51 CPU trace/debug connections from P8 to the FPGA. Table 2-19: CPU Trace/Debug Connection to FPGA Pin Name FPGA Pin (U37) Connector Pin (P8) ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 52 Chapter 2: ML410 Embedded Development Platform Table 2-19: CPU Trace/Debug Connection to FPGA (Cont’d) Pin Name FPGA Pin (U37) Connector Pin (P8) ATCB_CLK TRC_CLK CPU_HALT_N AH17 CPU_TDO TRC_VSENSE CPU_TCK AJ27 CPU_TMS ATD_18 AH13 CPU_TDI AK29 ATD_17 AJ11 CPU_TRST_N AH27 ATD_16...

  • Page 53: Cpu Jtag Header Pinout

    Table 2-20: CPU JTAG Connection to FPGA Pin Name FPGA Pin (U37) Connector Pin (J12) CPU_TDO CPU_TDI AK29 CPU_TRST_N AH27 CPU_TCK AJ27 CPU_TMS CPU_HALT_N AH17 ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 54: Vga Output

    Chapter 2: ML410 Embedded Development Platform VGA Output A VGA DB15HD connector (P2) is present on ML410 platforms to support an external video monitor. The VGA circuitry utilizes a 140 MHz, 24-bit color video DAC (Analog Devices ADV7125KST140). Table 2-21 shows the connections between the FPGA and the DAC.

  • Page 55: Pci Express

    Detailed Description PCI Express ML410 platforms that are equipped with PCI Express host connectors (P53 and P54) are capable of supporting PCI Express cores. Power distribution is handled by a MIC2959B dual-slot PCI Express hot-plug controller (Figure 2-16) that also provides comprehensive system protection and fault isolation.
  • Page 56 Chapter 2: ML410 Embedded Development Platform Table 2-22 Table 2-23, page 57 detail the connections between the FPGA and the PCI Express connectors. Table 2-22: Connections from FPGA to PCI Express Slot A Net Name FPGA Pin (U37) Connector Pin (P53)

  • Page 57: Pci Bus

    PCI Local Bus Specification, Revision 2.2 (see www.pcisig.com). The majority of the ML410 features are accessed over the 33 MHz/32-bit PCI bus. The Virtex-4 PPC405 processors can access the primary PCI bus through the EDK PCI Host Bridge IP.
  • Page 58 PCI slot pinouts, refer to the PCI Local Bus Specification, Revision 2.2 or review the ML410 schematics. Note: The 5V PCI slots differ from the 3.3V slots. See the Important Instructions sheet (PN 0402395) packaged with the ML410 kit before using Universal PCI add-in cards with ML410 platforms. PCI-to-PCI 3.3V...
  • Page 59 PCI Grant Signals PCI_GNT1_N PCI_GNT2_N PCI_GNT3_N PCI_GNT4_N PCI_CBE[0] PCI Byte-Enable Signals PCI_CBE[1] PCI_CBE[2] PCI_CBE[3] PCI_FRAME_N PCI Control Signals PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_DEVSEL_N PCI_PERR_N PCI_SERR_N PCI_LOCK PCI_IDSEL ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 60 Chapter 2: ML410 Embedded Development Platform Table 2-24: PCI Controller Connections (Cont’d) UCF Signal Name FPGA Pin (U37) Description PCI_AD[0] PCI Address/Data Lines PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17]...
  • Page 61 Detailed Description Table 2-25 shows how the primary PCI bus interrupts are connected on ML410 platforms along with information for each device. Table 2-25: 3.3V Primary PCI Bus Information PCI Interrupts on FPGA FPGA Device Name Dev. ID Vend. ID Bus DEV IDSEL REQ...

  • Page 62: Ali South Bridge Interface, M1535D+ (U15)

    PCI bus because this is the only way to access the ALI M1535D+. A brief description of the ALi M1535D+ features employed on ML410 platforms follows. Please review the ALi M1535D+ data sheet located on the ML410 documentation CD for more information.

  • Page 63: Parallel Port Interface Connector Assembly (P1)

    (see www.usb.org) that contains two PCI Host Controllers and an integrated Root Hub. The two USB connectors, A/B, are part of the J3 connector assembly and are USB Type-A plugs. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 64: Ide Connectors (J15 And J16)

    Chapter 2: ML410 Embedded Development Platform Table 2-28 shows the ALi USB connections to the two USB Type-A plugs (J3). Table 2-28: ALi South Bridge Connections to USB Type-A Signal Name A/B Pin (J3) Description USB_VCC USB Power, 5V, MOSFET Isolated...
  • Page 65 PIDE_DIOR SIDE_DIOR PIDE_IORDY SIDE_IORDY PIDE_CSEL SIDE_CSEL PIDE_DMACK_N SIDE_DMACK_N PIDE_INTRQ SIDE_INTRQ PIDE_A1 SIDE_A1 PIDE_PDIAG_N SIDE_PDIAG_N PIDE_A0 SIDE_A0 PIDE_A2 SIDE_A2 PIDE_CS1_N SIDE_CS1_N PIDE_CS3_N SIDE_CS3_N PIDE_DASP_N SIDE_DASP_N ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 66: Gpio Connector (J5)

    Chapter 2: ML410 Embedded Development Platform GPIO Connector (J5) There are 15 GPIO pins connecting the ALi M1535D+ to the 24-pin GPIO header (J5). These can be accessed through the ALi M1535D+ by way of the PCI bus. Table 2-30 shows the types and number of GPIO signals available to the user from the ALi South Bridge.

  • Page 67: Ac'97 Audio Interface

    ♦ MIDI MPU-401 interface ML410 platforms employ a National Semiconductor LM4550 audio codec (U1) combined with the ALi South Bridge AC’97 interface. This interface can be used to play and record audio. The LM4550 has left and right channel line inputs, left and right CD-ROM inputs, a microphone input, left and right channel line outputs, and an amplified headphone output suitable for driving an 8Ω...

  • Page 68: Ps/2 Keyboard And Mouse Interface Connector (P2)

    The ALi South Bridge has a flash memory interface port that supports up to 4 Mb of flash memory. ML410 platforms provide connectivity to an AM29F040B 4 Mb (512 K x 8 bit) flash memory (U4) via the ALi M1535D+ ROM interface.

  • Page 69: Iic/Smbus Interface

    High to 5V, although some devices support lower voltages. Either the master device or a slave device can drive either of the signals Low to transmit data or clock signals. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 70: Iic/Smbus On Ml410 Platforms

    Chapter 2: ML410 Embedded Development Platform IIC/SMBus on ML410 Platforms Table 2-35 lists the function, part number, and addresses of the IIC devices on ML410 platforms. These devices include EEPROM, temperature sensors, power monitors, and a Real Time Clock. Table 2-35: IIC and SMBus Controller Connections...
  • Page 71 24LC64 DDR2 DIMM P48 EEPROM ADDR: 0xA8 Front Panel Header MIC2592B PCIe Pwr Ctlr ADDR: 0x8E UG085_18_033007 Figure 2-19: IIC and SMBus Block Diagram ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 72: Serial Peripheral Interface

    Chapter 2: ML410 Embedded Development Platform Table 2-36 lists the IIC devices and their associated addresses. Table 2-36: IIC Devices and Addresses Reference Device Address Description Designator SMBus accelerator that ensures data integrity with multiple devices on the SMBus. Enhances data...

  • Page 73: Spi Addressing

    SPI_DATA_CS_N Serial ATA ML410 platforms provide two Serial ATA (SATA) host port connections via J25 and J26. Each SATA host port connection provides AC-coupled connections to and from an MGT on the FPGA. A 300 MHz differential reference clock is provided for use with the SATA MGTs and logic used to support the SATA protocol.

  • Page 74: Pushbuttons, Switches, Front Panel Interface, And Jumpers

    Chapter 2: ML410 Embedded Development Platform capacitors and resistors to AC-couple the signals. These connections are also shown in Table 2-38. Table 2-38: Connections Between FPGA and Serial ATA Connector (J25 and J26) Signal Name FPGA Pin (U37) Serial ATA Pin...

  • Page 75: Switches

    74. This can be accomplished by simply holding down the SW2 pushbutton for longer than two seconds. This action performs a CPU reset followed by a System ACE CF reset. See the ML410 schematics and the LTC1236 data sheet on the ML410 documentation CD for more details.
  • Page 76 Chapter 2: ML410 Embedded Development Platform 2.5V System ACE (U38) Shown here with CFGADDR[2:0] System ACE CFG RESET set to 000 (default) ON => SW Closed SYSACE_RESET_N Debounce System ACE Reset CFGADDR[2:0] = Default UG085_20_120505 Figure 2-21: SW3: System ACE Configuration Switch Detail...

  • Page 77: Front Panel Interface (J23)

    (0.1 inch pitch). J23 provides an optional means to control and gather status information from the ML410 if enclosed in a case similar to a desktop computer. The functionality listed below can easily be connected with a custom user-provided cable that connects to user logic designed to control and monitor the functionality available through the front panel interface.
  • Page 78 Chapter 2: ML410 Embedded Development Platform Table 2-41 shows the signals available at the front panel interface header (J23). Table 2-41: Front Panel Interface Connector (J23) Schematic Signal Description SYACE_CFGA0 Used to select System ACE configuration, CFGADDR0 User defined function, connects to the FPGA, U37-G15, FPGA_LED_USER1 (2.5V bank)

  • Page 79: Jumpers

    To avoid contention after the FPGA is configured, this functionality should not be used if logic that also drives the CPU JTAG connector (J12) or the FPGA JTAG/TRACE connector (P8) is implemented. ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 80: Atx Power Distribution And Voltage Regulation

    ATX Power Distribution and Voltage Regulation ML410 platforms are shipped with a commercially available 250W ATX power supply. All voltages required by the ML410 logic devices are derived from the 5V supply, except the ±12V supplies, as shown in Figure 2-22.
  • Page 81 Detailed Description The different logic devices used on the ML410 platforms require a variety of voltages. Voltage levels are derived from the 5V supply and regulated on the board as shown in Figure 2-22. VCC5V VCC3_PCI LT1763CS8 (3V @ 500 mA)
  • Page 82 LED. See the ML410 schematics and the associated data sheets for more information. In addition to the voltage monitors, the ML410 employs a SMBus device, LM87, which samples several of the same supply voltages when accessed over the System Management Bus.
  • Page 83 Direct from ATX power supply VCC12V_N –12V TP19 Direct from ATX power supply Notes: 1. Green LED = Voltage Nominal; Red LED = Voltage Fault ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...

  • Page 84: High-Speed I/O

    1367550-5 data sheet at Tyco’s website (www.z-dok.com). The ML410 is the host board, functioning as the development platform for the Virtex-4 FX FPGA. The PM connectors on the ML410 platforms provide a means for extending the functionality of the board through high-speed I/O pins.

  • Page 85: Personality Module Connectors

    2-26. The signal pairs alternate from side to side along the length of the divider. All of the B and E pins are grounded on the ML410. The A, C, D, and F pins are signal pins. Copper Pins Plastic Divider...

  • Page 86: Pm1 Connector

    Row F F – F = 0 – 0 Notes: 1. All offsets are normalized to row F. The ML410 design is based on the data in the Offset/2 column. PM1 Connector The PM1 connector provides the following signals: •...

  • Page 87: Z-Dok+ Utility Pins

    Figure 2-27: Adapter Board Connector Pin Detail Z-DOK+ Utility Pins Figure 2-28 shows the Z-DOK+ utility pins and numbering for the host board PM connector. UG085_27_112105 Figure 2-28: Z-DOK+ Utility Pins (ML410 Side) ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

  • Page 88: Contact Order

    2 and 5; • then 3 and 4 PM1 Power and Ground Table 2-47 shows the power and ground pins for the PM1 connector on the ML410. Table 2-47: PM1 Power and Ground Pins Pin Number Description Length Contact Order...

  • Page 89: Pm User I/O Pins

    PM_IO_3V_16 Single-ended 50Ω impedance IO_L14P_12 PM_IO_3V_12 Single-ended 50Ω impedance IO_L12N_VREF_12 PM_IO_3V_1 Single-ended 50Ω impedance IO_L12P_12 PM_IO_3V_3 Single-ended 50Ω impedance IO_L27N_12 PM_IO_3V_17 Single-ended 50Ω impedance ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 90 Chapter 2: ML410 Embedded Development Platform Table 2-48: PM1 Pinout (Cont’d) FPGA ML410 Schematic FPGA Bank PM1 Pin Pin Description Pin Function Pin (U37) IO_L27P_12 PM_IO_3V_5 Single-ended 50Ω impedance AF15 IO_L17P_8 PM_IO_80 2.5V LVDS pair 100Ω differential impedance; can also be used as...

  • Page 91: Pm2 User I/O

    PM2 User I/O The PM2 connector makes most of the LVDS pairs available to the user, along with single- ended signals. Table 2-49 shows the pinout for the PM2 connector on the ML410. Table 2-49: PM2 Pinout FPGA ML410 FPGA Bank...
  • Page 92 Chapter 2: ML410 Embedded Development Platform Table 2-49: PM2 Pinout (Cont’d) FPGA ML410 FPGA Bank PM2 Pin Pin Description Pin Function Pin (U37) Schematic Net VCCO AM12 IO_L30N_8 PM_IO_67 2.5V LVDS pair 100Ω differential impedance; can also be used as...
  • Page 93 AK23 IO_L16P_7 PM_IO_48 2.5V single-ended AK32 IO_L1P_7 PM_IO_74 2.5V LVDS pair 100Ω differential impedance; can also be used as AK31 IO_L1N_7 PM_IO_75 2.5V single-ended ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 94 Chapter 2: ML410 Embedded Development Platform Table 2-49: PM2 Pinout (Cont’d) FPGA ML410 FPGA Bank PM2 Pin Pin Description Pin Function Pin (U37) Schematic Net VCCO AE22 IO_L12P_7 PM_IO_20 2.5V LVDS pair 100Ω differential impedance; can also be used as...
  • Page 95 PM_IO_3 2.5V single-ended AD24 IO_L28P_7 PM_IO_16 2.5V LVDS pair 100Ω differential impedance; can also be used as AE24 IO_L28N _VREF _7 PM_IO_17 2.5V single-ended ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 96 Chapter 2: ML410 Embedded Development Platform www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 97 1. Board revision markings are located in the corner of the board near the gold Xilinx logo. 2. ML410-P Rev. D boards with CES4 devices support up to 3.125 Gb/s RocketIO transceiver interfaces, while Rev. E boards with CES4S devices upport up to 6.5 Gb/s. Refer to the Virtex-4 Errata for more details regarding Virtex-4 FX silicon errata.
  • Page 98 (MGT Left Side) 25 MHz 150 MHz LVDS_CLKEXT_P (From PM Interface) (MGT Right Side) ICS844001-1 LVDS_CLKEXT_N UG085_APDX_A_01_101006 Figure A-1: Clock Distribution for Revisions C and D www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 99 SATACLK_NQ0 (Fixed) AP28 150 MHz Serial ATA clock. Notes: 5. These clocks are differential pairs through the RocketIO transceivers and are not available on ML410-P boards. See Figure A-1, page ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...
  • Page 100 ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com electronic components distributor...
  • Page 101 DS302, Virtex-4 Data Sheet UG076, Virtex-4 RocketIO Transceiver User Guide DS080, System ACE CompactFlash Solution. UG070, Virtex-4 User Guide UG074, Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide ML410 Embedded Development Platform www.xilinx.com UG085 (v1.7.2) December 11, 2008 Downloaded from Elcodis.com...

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