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Table 2-49: PM2 Pinout (Cont'd)
FPGA
PM2 Pin
Pin (U37)
D19
AE28
D20
AF28
F1
AH25
F2
AG25
F3
AL13
F4
AK13
F5
AK24
F6
AL24
F7
AM25
F8
AL25
F9
NC
F10
AD21
F11
AL10
F12
AM10
F13
AK28
F14
AL28
F15
AC23
F16
AC22
F17
AL31
F18
AL30
F19
AD24
F20
AE24
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Pin Description
Schematic Net
IO_L19P_7
IO_L19N_7
IO_L29N
_SM4 _7
IO_L29P
_SM4 _7
IO_L32N_8
IO_L32P_8
IO_L22N_7
IO_L22P_7
IO_L26N
_SM6 _7
_SM6 _7
IO_L26P
NC
_LC _4
IO_L1P_GC
PM_CLK_BOT
IO_L16P_8
IO_L16N_8
IO_L15P_7
IO_L15N_7
IO_L4P_7
IO_L4N_VREF_7
IO_L5P_7
IO_L5N_7
IO_L28P_7
IO_L28N
_VREF _7
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ML410
FPGA Bank
VCCO
PM_IO_12
2.5V
PM_IO_13
2.5V
PM_IO_41
2.5V
PM_IO_40
2.5V
PM_IO_65
2.5V
PM_IO_64
2.5V
PM_IO_47
2.5V
PM_IO_46
2.5V
PM_IO_37
2.5V
PM_IO_36
2.5V
NC
2.5V
2.5V
PM_IO_6
2.5V
PM_IO_7
2.5V
PM_IO_30
2.5V
PM_IO_31
2.5V
PM_IO_18
2.5V
PM_IO_19
2.5V
PM_IO_2
2.5V
PM_IO_3
2.5V
PM_IO_16
2.5V
PM_IO_17
2.5V
High-Speed I/O
Pin Function
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
No Connect
Clock
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
LVDS pair 100Ω differential
impedance; can also be used as
single-ended
95
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