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Chapter 1: Introduction to Virtex-4, ISE, and EDK
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This rich mixture of design entry capabilities provides the easiest to use design
environment available today for your logic design.
Synthesis
Synthesis is one of the most essential steps in your design methodology. It takes your
conceptual Hardware Description Language (HDL) design definition and generates the
logical or physical representation for the targeted silicon device.
A state-of-the-art synthesis engine is required to produce highly optimized results with a
fast compile and turnaround time. To meet this requirement, the synthesis engine needs to
be tightly integrated with the physical implementation tool and have the ability to
proactively meet the design timing requirements by driving the placement in the physical
device. In addition, cross probing between the physical design report and the HDL design
code further improves the turnaround time.
Xilinx ISE provides the seamless integration with the leading synthesis engines from
Mentor Graphics, Synopsys, and Synplicity. You can use the synthesis engine of our
choice. In addition, ISE includes Xilinx proprietary synthesis technology, XST. You have
options to use multiple synthesis engines to obtain the best-optimized result of your
programmable logic design.
Implementation and Configuration
Programmable logic design implementation assigns the logic created during design entry
and synthesis into specific physical resources of the target device.
The term "place and route" has historically been used to describe the implementation
process for FPGA devices and "fitting" has been used for CPLDs. Implementation is
followed by device configuration, where a bitstream is generated from the physical place
and route information and downloaded into the target programmable logic device.
To ensure designers get their product to market quickly, Xilinx ISE software provides
several key technologies required for design implementation:
•
Ultra-fast runtimes enable multiple "turns" per day
•
ProActive™ Timing Closure drives high-performance results
•
Timing-driven place and route combined with pushbutton ease
•
Incremental Design
Board-Level Integration
Xilinx understands the critical issues such as complex board layout, signal integrity, high-
speed bus interface, high-performance I/O bandwidth, and electromagnetic interference
for system-level designers.
To ease the system level designers' challenge, ISE provides support to all Xilinx leading
FPGA technologies:
•
System IO
•
XCITE
•
Digital clock management for system timing
•
EMI control management for electromagnetic interference
To ensure that your programmable logic design works in the context of your entire system,
Xilinx provides complete pin configurations, packaging information, tips on signal
integration, and various simulation models for your board-level verification including:
www.xilinx.com
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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