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Volume 2(a):

PPC405 User Manual

Virtex-II Pro™ Platform FPGA

Developer's Kit

March 2002 Release

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Page 1 Volume 2(a): PPC405 User Manual Virtex-II Pro™ Platform FPGA Developer’s Kit March 2002 Release...
Page 2 All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible.
Page 3 PPC405. • Chapter 9, Debugging, describes the debug resources available to software and hardware debuggers. • Chapter 10, Reset and Initialization, describes the state of the PPC405 following reset March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 4 The contents of the register rA, or 0 if the rA instruction field is 0. cr_bit Used in simplified mnemonics to specify a CR-bit position (0 to 31) used as an operand. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 5: Instruction Fields
Specifies a bit in the CR used as a source of a CR-logical instruction. crbD 6:10 Specifies a bit in the CR used as a destination of a CR-Logical instruction. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 6 Condition Register (CR), page 361 for a further discussion of how the CR bits are set. 6:10 Specifies a GPR destination operand. 6:10 Specifies a GPR source operand. 16:20 Specifies a shift amount. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 7: Pseudocode Conventions
Remainder of an integer division. For example, (33 % 32) = 1. Concatenation =, ≠ Equal, not-equal relations <, > Signed comparison relations Unsigned comparison relations < > A four-bit object used to store condition results in compare instructions. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 8 Reserve bit. Indicates whether a process has reserved a block of storage. ROTL((RS),n) Rotate left. The contents of RS are shifted left the number of bits specified by n . SPR(SPRN) A specific special-purpose register, as indicated by SPRN. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 9: Operator Precedence
Register Descriptive Name CCR0 Core-configuration register 0 Condition register Count register DACn Data-address compare n DBCRn Debug-control register n DBSR Debug-status register DCCR Data-cache cacheability register DCWR Data-cache write-through register March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 10 The term refers to the fact that such transactions are indivisible. big endian A memory byte ordering where the address of an item corresponds to the most-significant byte. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 11 Megabyte, or one-million bytes. memory Collectively, cache memory and system memory. miss For cache arrays and TLB arrays, an indication that requested information does not exist in the accessed array. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 12 The operating mode typically used by application software. Privileged operations are not allowed in user mode, and software can access a restricted set of registers and memory. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 13: Additional Reading
Optimizing PowerPC Code : Programming the PowerPC Chip in Assembly Language, by Gary Kacmarcik (ASIN: 0201408392) • PowerPC Programming Pocket Book, by Steve Heath (ISBN 0750621117). • Computer Architecture: A Quantitative Approach, by John L. Hennessy and David A. Patterson. • March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 14 Preface www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 15: Introduction To The Ppc405
The memory model defines the address-space size and how it is subdivided into pages. It also defines attributes for specifying memory-region cacheability, byte ordering (big- endian or little-endian), coherency, and protection. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 16: Powerpc Architecture Levels
PowerPC application programs. However, different versions of the VEA and OEA are permitted. Embedded applications written for the PPC405 are compatible with other PowerPC implementations. Privileged software generally is not compatible. The migration of www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 17 The architecture does not define details regarding the instruction- fetch mechanism, how instructions are decoded and dispatched, and how results are written to registers. Dispatch and write-back can occur in-order or out-of-order. Although March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 18: Powerpc Embedded-Environment Architecture
Memory management optimized for embedded software environments. • Cache-management instructions for optimizing performance and memory control in complex applications that are graphically and numerically intensive. • Storage attributes for controlling memory-system behavior. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 19 (optional), guarded, and endian. Operand-placement requirements and their effect on performance. • The time-base function as defined by the PowerPC virtual-environment architecture, for user-mode read access to the 64-bit time base. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 20 Specification for two internal mechanisms that can cause a reset: Reset and initialization requirements Debug-control register (DBCR) Timer-control register (TCR) • Contents of processor resources after a reset • The software-initialization requirements, including an initialization code example www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 21: Powerpc Book-E Architecture
Static branch prediction Five-stage pipeline with single-cycle execution of most instructions, including loads and stores Multiply-accumulate instructions Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) Enhanced string and multiple-word handling March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 22: Privilege Modes
Software running on the PPC405 can do so in one of two privilege modes: privilieged and user. The privilege modes supported by the PPC405 are described in Processor Operating Modes, page 343. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 23: Address Translation Modes
Branch-Target Address Calculation, page 372. Data Types PPC405 instructions support byte, halfword, and word operands. Multiple-word operands are supported by the load/store multiple instructions and byte strings are supported by March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 24: Register Set Summary
347, for more information on the supported data types and byte ordering. Register Set Summary Figure 1-2, page 333 shows the registers contained in the PPC405. Descriptions of the registers are in the following sections. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 25 GPRs and write their results in GPRs. Other instructions move data between the GPRs and other registers. GPRs can be accessed by all software. See General- Purpose Registers (GPRs), page 360, for more information. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 26: Ppc405 Organization
• Separate instruction-cache and data-cache units • Debug support, including a JTAG interface • Three programmable timers The following sections provide an overview of each element. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 27 During the write-back stage, results are written to the GPR. The use of five read/write ports on the GPRs allows the processor to execute load/store operations in parallel with ALU and MAC operations. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 28 Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 29 (See Chapter 8, Timer Resources, for more information on these features.) The three timers supported by the PPC405 are: • Programmable Interval Timer • Fixed Interval Timer • Watchdog Timer March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 30 Two of the 64-bit buses are attached to the data-cache unit, one supporting read operations and the other supporting write operations. The third 64-bit bus is attached to the instruction-cache unit to support instruction fetching. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 31 On-Chip Memory Controller An on-chip memory (OCM) interface supports the attachment of additional memory to the instruction and data caches that can be accessed at performance levels matching the cache arrays. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 32 Chapter 1: Introduction to the PPC405 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 33: Operational Concepts
PPC405 to a processor that supports multiprocessor memory coherency and speculative loads. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 34: Synchronization Operations
(sync) instruction, the sync does not complete execution until all prior instructions complete execution to a point where they report any exceptions they cause to occur. The sync and move-to machine-state register (mtmsr) instructions are examples of execution- synchronizing instructions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 35: Storage Synchronization
Table 4-3, page 434. The operation of each instruction is described in Chapter 11, Instruction Set. Privileged mode is sometimes referred to as supervisor state. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 36: User Mode
All effective-address computations are performed by the processor using unsigned binary arithmetic. Carries from bit 0 are ignored and the effective address wraps from the maximum address (2 -1) to address 0 when the calculation overflows. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 37: Physical Memory
4 KB. • The PPC405 does not support the segment-translation mechanism defined by the PowerPC architecture. • The PPC405 does not support the block-address-translation (BAT) mechanism defined by the PowerPC architecture. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 38 (DR) field in the MSR. When MSR[DR] = 0, data accesses are performed in real mode. Setting MSR[DR] = 1 enables virtual mode for data accesses. See Virtual Mode, page 472 for more information on these fields. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 39: Operand Conventions
The memory operand appears on the left in this diagram and the equivalent register representation appears on the right. The following sections describe the concepts of byte ordering and data alignment, and their significance to the PowerPC PPC405. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 40 Memory Address Byte 1 0x01 Byte 0 0x00 Memory Content Byte Register Content Byte 0 0x04 0x03 0x02 Memory Address 0x01 Byte 0 0x00 UG011_14_100901 Figure 2-2: Operand Data Types www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 41: Byte Ordering
The same amount of padding is present in both big-endian and little- endian mappings. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 42 Memory-address modification restricts how the processor can access misaligned data and I/O. The PPC405 little-endian support does not have these restrictions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 43 If the endian-storage attribute is changed, the affected memory region must be reloaded with program and data structures using the new endian ordering. If the endian ordering of March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 44 However, compilers can take full advantage of the E storage- attribute mechanism, allowing application programmers working in a high-level language, such as C, to compile programs and data structures using little-endian ordering. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 45: Operand Alignment
This table applies to both big-endian and little-endian accesses. Figure 2-2 also applies to PowerPC processors running in the default big-endian mode. However, those same processors suffer further performance degradation when running in PowerPC little- endian mode. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 46: Instruction Conventions
The formats used for the instructions of the PowerPC embedded-environment architecture are shown in Instructions Grouped by Form, page 792. The Instruction Set Information, page 797 also shows the form used by each instruction, listed alphabetically by mnemonic. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 47: Instruction Classes
(normally cleared to 0) produces an invalid instruction form. The following instructions have invalid forms: • Branch-conditional instructions • Load with update and store with update instructions • Load multiple instructions March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 48 PPC405 and other PowerPC embedded-environment family implementations. From the standpoint of the PowerPC architecture, these instructions are part of the reserved class and are implementation www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 49: Powerpc Book-E Instruction Classes
Allocated Book-E Instruction Class The allocated instruction class contains the set of instructions used for implementation- dependent and application-specific use, outside the scope of the PowerPC Book E architecture. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 50 Preserved Book-E Instruction Class The preserved instruction class is provided to support backward compatibility with previous generations of this architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 51: User Programming Model
In the PPC405, all user registers are 32-bits wide, except for the time base as described in Time Base, page 524. Floating-point registers are not supported by the PPC405. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 52: Special-Purpose Registers (Sprs)
GPRs are written to memory using store instructions. Most integer instructions use the GPRs for source and destination operands. Figure 3-2: General Purpose Registers (R0-R31) www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 53: Condition Register (Cr)
The fourth bit of CR0 (CR0[3]) is copied from XER[SO]. The CR0 bits are interpreted as described in Table 3-1. If any portion of the result is undefined, the value written into CR0[0:2] is undefined. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 54 A is equal. otherwise it is cleared. Summary overflow This is a copy of the final state of XER[SO] at the completion of the instruction. 0—No overflow occurred. 1—Overflow occurred. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 55: Fixed-Point Exception Register (Xer)
The link-register update-option is enabled when the branch-instruction LK opcode field (bit 31) is set to 1. The format of LR is shown in Figure 3-6. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 56: Count Register (Ctr)
The value stored in this register does not have an effect on the operation of the PPC405 processor. The format of USPRG0 is shown in Figure 3-8. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 57: Spr General-Purpose Registers
Reading the time-base registers requires use of the mftb instruction with the following addresses: • TBU—269 (0x10D). • TBL—268 (0x10C). Time Base, page 524, for information on using the time base. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 58: Exception Summary
System-Call Exception. The execution of an sc instruction causes the system-call interrupt handler to be invoked. The interrupt handler can be used to call a system-service routine. • Data TLB-Miss Exception. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 59: Branch And Flow-Control Instructions
0—Test the CR bit specified by the BI opcode field for the value indicated by BO[1]. 1—Do not test the CR. BO[1] CR Test Value 0—Test for CR[BI]=0. 1—Test for CR[BI]=1. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 60 24-bit LI instruction field with 0b00. The displacement value gives unconditional branches the ability to cover an address range of ±32 MB. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 61 Branch-conditional to address in LR. BO,BI bclrl Branch Conditional to Link Register Branch-conditional to address in LR. LR is updated and Link with the address of the instruction following the branch. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 62: Branch Prediction
For the bcx instruction with a negative value in the displacement operand, the branch is predicted taken. • For all other branch-conditional instructions (bcx with a non-negative value in the displacement operand, bclrx, or bcctrx), the branch is predicted not taken. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 63 (LK=0) to branch to the selected address. • Direct subroutine linkage, where A calls B and B returns to A: A calls B—use a branch instruction that enables the LR (LK=1). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 64: Branch-Target Address Calculation
LR. Figure 3-11 shows how the branch-target address is generated when using the branch-to- relative addressing mode. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 65 Instruction Encoding Condition Sign Extension Met? Next Sequential Instruction Address Current Instruction Address Branch Target Address UG011_07_033101 Figure 3-12: Branch-Conditional to Relative Addressing March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 66 Instruction Encoding Condition Sign Extension Met? Next Sequential Instruction Address Branch Target Address UG011_08_033101 Figure 3-14: Branch-Conditional to Absolute Addressing www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 67 Instruction Encoding 00000 Condition Met? Next Sequential Instruction Address Branch Target Address UG011_10_033101 Figure 3-16: Branch-Conditional to Count-Register Addressing March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 68: Condition-Register Logical Instructions
System-Call Interrupt (0x0C00), page 514 for more information on the operation of this instruction. Table 3-11: System-Call Instruction Operand Mnemonic Name Operation Syntax System Call Causes a system-call exception to occur. — www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 69: System Trap
Less-than arithmetic comparison. 0—Ignore trap condition. 1—Trap if first operand is arithmetically less-than second operand. TO[1] Greater-than arithmetic comparison. 0—Ignore trap condition. 1—Trap if first operand is arithmetically greater-than second operand. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 70: Integer Load And Store Instructions
0 (specifying r0), a value of zero—rather than the contents of r0—is added to the sign-extended immediate index. The option to specify rA or 0 is shown in the instruction description as (rA|0). www.xilinx.com March 2002 Release 1-800-255-7778...
Page 71 The option to specify rA or 0 is shown in the instruction description as (rA|0). Figure 3-18 shows how an effective address is generated when using register-indirect with index addressing. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 72 Instruction Encoding Opcode rD/rS Subopcode rA=0? 0000 0000 0000 0000 0000 0000 0000 0000 (rA) Effective Address UG011_03_033101 Figure 3-19: Register-Indirect Addressing www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 73: Load Instructions
PowerPC load halfword and zero instructions. These instructions load a halfword from memory into the lower-16 bits of rD and clear the upper-16 bits of rD to 0. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 74 PowerPC load halfword algebraic instructions. These instructions load a halfword from memory into the lower-16 bits of rD. The upper-16 bits of rD are filled with a copy of the most-significant bit (bit 16) of the operand. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 75 EA = (rA|0) + (rB) lhaux Load Halfword Algebraic with Register-indirect with index Update Indexed EA = (rA) + (rB) rA ← EA rA ≠ 0, rA ≠ rD March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 76: Store Instructions
← EA rA ≠ 0 Store Halfword Table 3-19 lists the PowerPC store halfword instructions. These instructions store the lower- 16 bits of rS into the specified halfword location in memory. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 77: Load And Store With Byte-Reverse Instructions
When used in a system operating with the default big-endian byte order, these instructions have the effect of loading and storing data in little-endian order. Likewise, when used in a system operating with little-endian byte order, these instructions have the effect of loading March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 78: Load And Store Multiple Instructions
These instructions are used to move blocks of data between memory and the GPRs. When the load multiple word instruction (lmw) is executed, rD through r31 are loaded with n www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 79: Load And Store String Instructions
PowerPC load and store string instructions and their addressing modes. See the individual instruction listings in Chapter 11, Instruction Set for more information on their operation and restrictions on the instruction forms. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 80 For loads, any unfilled low-order register bytes are cleared to 0. The sequence of registers loaded or stored wraps through r0 if necessary. Figure 3-22 shows an example of the string-instruction operation. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 81: Integer Instructions
The arithmetic, shift, and rotate instructions can update and/or read bits from the XER. Those instructions, plus the integer-logical instructions, can also update bits in the CR. Unless otherwise noted, when XER and/or CR are updated, they reflect the value written March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 82: Arithmetic Instructions
CR0 is updated to reflect the result. addo Add with Overflow Enabled XER[OV,SO] are updated to reflect the result. addo. Add with Overflow Enabled and XER[OV,SO] and CR0 are updated to reflect the Record result. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 83 Add to Minus One Extended with XER[CA,OV,SO] are updated to reflect the result. Overflow Enabled addmeo. Add to Minus One Extended with XER[CA,OV,SO] and CR0 are updated to reflect Overflow Enabled and Record the result. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 84 Subtract from with Overflow Enabled XER[OV,SO] are updated to reflect the result. subfo. Subtract from with Overflow Enabled XER[OV,SO] and CR0 are updated to reflect the and Record result. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 85 For each instruction shown, the “Operation” column indicates (on an instruction-by-instruction basis) how the XER and CR registers are updated (if at all). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 86 Multiply High Word rD,rA,rB XER and CR0 are updated. Multiply High Word and Record mulhwu. CR0 is updated to reflect the result. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 87: Logical Instructions
PowerPC AND and NAND instructions. For each type of instruction shown, the “Operation” column indicates the Boolean operation performed. The column also shows, on an instruction-by-instruction basis, whether the CR0 field is updated. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 88 CR0 is updated. OR and Record CR0 is updated to reflect the result. OR-Immediate Instructions rA is loaded with the logical result (rS) OR UIMM. OR Immediate rA,rS,UIMM CR0 is updated. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 89 For each type of instruction shown, the “Operation” column indicates the operation performed. The column also shows, on an instruction-by-instruction basis, whether the CR0 field is updated. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 90 See Compare Instructions, page 828 for more information. The last two operands specify the quantities to be compared (the contents of a register and a register or immediate value). www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 91: Rotate Instructions
Simplified mnemonics using the rotate instructions are provided for easy coding of extraction, insertion, left or right justification, and other bit-manipulation operations. See Rotate and Shift Instructions, page 829 for more information. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 92 Rotate Left Word Immediate then rA,rS,SH,MB,ME CR0 is updated. AND with Mask rlwinm. Rotate Left Word Immediate then CR0 is updated to reflect the result. AND with Mask and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 93 Rotate Left then Mask-Insert Instructions Table 3-36 shows the PowerPC rotate left then mask-insert instructions. For each type of instruction shown, the “Operation” column indicates the rotate operation performed. The March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 94 0x66 0x55 Rotate 0x66 0x55 0x88 0x77 Rotate by SH=16 bits Mask MB=16 0000_0000 0000_0000_0000_0000 1111_1111 ME=23 0xFF 0xEE 0x88 0xCC UG011_17_033101 Figure 3-25: Rotate Left then Mask-Insert Immediate Example www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 95: Shift Instructions
As is seen in these examples, bits shifted out of the register are lost and vacated bits are filled with zeros. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 96 Shift Right Algebraic Word Immediate rA,rS,SH CR0 is updated. XER[CA] is updated to reflect the result. srawi. Shift Right Algebraic Word Immediate CR0 and XER[CA] are updated to reflect the re- and Record sult. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 97: Multiply-Accumulate Instruction-Set Extensions
With saturating-arithmetic instructions, the low 32-bits of the intermediate result are stored in the destination register if the intermediate result does not overflow 32-bits. However, if the intermediate result overflows what is representable in 32-bits, the March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 98: Multiply-Accumulate Instructions
Word Modulo Signed with Overflow Enabled macchwo. Multiply Accumulate Cross Halfword XER[OV,SO] and CR0 are updated to reflect the to Word Modulo Signed with result. Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 99 XER[OV,SO] and CR0 are updated to reflect the to Word Modulo Unsigned with result. Overflow Enabled and Record Figure 3-28 shows the operation of the integer multiply-accumulate cross-halfword to word instructions. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 100 Word Modulo Signed with Overflow Enabled machhwo. Multiply Accumulate High Halfword XER[OV,SO] and CR0 are updated to reflect the to Word Modulo Signed with result. Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 101 XER[OV,SO] and CR0 are updated to reflect the to Word Modulo Unsigned with result. Overflow Enabled and Record Figure 3-29 shows the operation of the multiply-accumulate high-halfword to word instructions. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 102 Table 3-42, the “Operation” column indicates the multiply-accumulate operation performed. The column also shows, on an instruction-by- instruction basis, how the XER and CR registers are updated (if at all). www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 103 Word Saturate Unsigned with Overflow Enabled maclhwsuo. Multiply Accumulate Low Halfword XER[OV,SO] and CR0 are updated to reflect the to Word Saturate Unsigned with result. Overflow Enabled and Record March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 104 Word Modulo Unsigned with Overflow Enabled maclhwuo. Multiply Accumulate Low Halfword XER[OV,SO] and CR0 are updated to reflect the to Word Modulo Unsigned with result. Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 105: Negative Multiply-Accumulate Instructions
Table 3-43, the “Operation” column indicates the negative multiply-accumulate operation performed. The column also shows, on an instruction-by-instruction basis, how the XER and CR registers are updated (if at all). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 106 Halfword to Word Saturate Signed with Overflow Enabled nmacchwso. Negative Multiply Accumulate Cross XER[OV,SO] and CR0 are updated to reflect the Halfword to Word Saturate Signed result. with Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 107 Table 3-44, the “Operation” column indicates the negative multiply-accumulate operation performed. The column also shows, on an instruction-by-instruction basis, how the XER and CR registers are updated (if at all). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 108 XER[OV,SO] and CR0 are updated to reflect the Halfword to Word Saturate Signed result. with Overflow Enabled and Record Figure 3-32 shows the operation of the negative multiply-accumulate high-halfword to word instructions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 109 Table 3-45, the “Operation” column indicates the negative multiply-accumulate operation performed. The column also shows, on an instruction-by-instruction basis, how the XER and CR registers are updated (if at all). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 110 Halfword to Word Saturate Signed with Overflow Enabled nmaclhwso. Negative Multiply Accumulate Low XER[OV,SO] and CR0 are updated to reflect the Halfword to Word Saturate Signed result. with Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 111: Multiply Halfword To Word Instructions
(rA[16:31]) (rB[0:15]). mulchw Multiply Cross Halfword to Word rD,rA,rB CR0 is updated. Signed mulchw. Multiply Cross Halfword to Word CR0 is updated to reflect the result. Signed and Record March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 112 (rA[0:15]) (rB[0:15]). mulhhw Multiply High Halfword to Word rD,rA,rB CR0 is updated. Signed mulhhw. Multiply High Halfword to Word CR0 is updated to reflect the result. Signed and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 113 (rA[16:31]) (rB[16:31]). mullhw Multiply Low Halfword to Word rD,rA,rB CR0 is updated. Signed mullhw. Multiply Low Halfword to Word CR0 is updated to reflect the result. Signed and Record March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 114: Floating-Point Emulation
In user mode, processor-control instructions are used to read from and write to the condition register (CR) and the special-purpose registers (SPRs). Instructions that access the time base are also considered processor-control instructions, but are discussed separately in Chapter 8, Timer Resources. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 115: Condition-Register Move Instructions
CRM field is used. In this example, CRM = 0b01100100, causing CR1, CR2, and CR5 to be updated with the corresponding bits in rS. All remaining CR fields are unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 116: Special-Purpose Register Instructions
The SPR specified by SPRN is loaded with the contents of rS. Synchronizing Instructions Table 3-51 lists the PowerPC synchronization instructions. The types of synchronization defined by the PowerPC architecture are described in Synchronization Operations, page 342. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 117: Implementation Of Eieio And Sync Instructions
Synchronization Effects of PowerPC Instructions Additional PowerPC instructions can cause synchronizing operations to occur. All instructions that result in some form of synchronization are listed in Table 3-52. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 118: Semaphore Synchronization
CR0[EQ] is set to 1. If the reservation does not exist when the store is executed, the target memory location is not modified and CR0[EQ] is cleared to 0. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 119: Memory-Control Instructions
Data Cache Block Store dcbt Data Cache Block Touch dcbtst Data Cache Block Touch for Store dcbz Data Cache Block Set to Zero icbi Instruction Cache Block Invalidate icbt Instruction Cache Block Touch March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 120 Chapter 3: User Programming Model www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 121 The zone-protection register (ZPR) is described in Virtual-Mode Access Protection, page 482. • The storage-attribute control registers are described in Memory-System Control, page 451. • The exception-handling registers are described in Interrupt-Handling Registers, page 497. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 122 Timer Registers SRR2 SPR 0x3DA Memory-Management SPR 0x3DF Registers SRR3 SPR 0x3B1 SPR 0x3D8 SPR 0x3B0 SPR 0x3DB Time-Base Registers SPR 0x11C SPR 0x11D UG011_33_033101 Figure 4-1: PPC405 Privileged Registers www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 123: Special-Purpose Registers
Reserved External Interrupt Enable Controls the external interrupts, the programmable-interval timer interrupt, and the fixed-interval timer interrupt. See Interrupt 0—Disabled. Reference, page 502, for more information on each interrupt. 1—Enabled. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 124 Four of the registers (SPRG4–SPRG7) are available from user mode with read-only access. Application software can read the contents of SPRG4–SPRG7, but cannot modify them. The format of all SPRGn registers is shown in Figure 4-3. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 125: Processor-Version Register
Figure 4-4: Processor-Version Register (PVR) Table 4-2: Processor-Version Register (PVR) Bit Definitions Name Function/Value Description 0:11 Owner Identifier Identifies Xilinx as the owner of the processor core. 0b 0010_0000_0000 (0x200) 12:15 Processor Core Family Identifies the processor as belonging to the 405 processor-core family.
Page 126: Privileged Instructions
Returns from the system-service routine reverse the process described above. Control is transferred back to the system-call interrupt handler using a branch to link-register www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 127 (SPRs) using a GPR as a destination or source register. The SPR number (SPRN) shown in the operand syntax column can be specified as a decimal or hexadecimal value in the assembler listing. Within the instruction opcode, this number is March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 128: Processor Wait State
The processor continues to respond to interrupts, and can be restarted through the use of external interrupts or timer interrupts. Wait state can also be exited when an external debug tool clears WE or when a reset occurs. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 129: Memory-System Management
System Memory Memory Controller Processor Local Bus I-Cache I-Cache D-Cache D-Cache Instruction Data Controller Array Array Controller Instruction-Cache Data-Cache Unit Unit Execute GPRs Processor UG011_42_021902 Figure 5-1: PPC405 Memory-System Organization March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 130: Memory-System Features
B make up a set of cachelines, also known as a congruence class. A cache array contains a total of 256 sets, or congruence classes. Each cacheline contains the following pieces of information: www.xilinx.com March 2002 Release 1-800-255-7778...
Page 131 The instruction cache is accessed in this manner for performance reasons, but care is required to avoid cache synonyms (see Instruction-Cache Synonyms, page 442). Figure 5-3 shows the address fields used in accessing the two caches. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 132 A hit occurs when the data- address tag field is equal to one of the two tags. A miss occurs when the data-address tag field is not equal to either of the tags. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 133: Instruction-Cache Operation
(full line) and is programmable using the CCR0 register (see Core-Configuration Register, page 459). Full-line (cacheable and non-cacheable) and half-line fetch requests are always completed (never aborted), even if the instruction stream branches before the March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 134 0x8888_8000 and 0xFFFF_F000, to the same physical address, 0x4444_4000 (see Chapter 6, Virtual-Memory Management for information on address translation). When a 4 KB page address is translated, the translation mechanism maps each effective-page number (EA 0:19 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 135: Data-Cache Operation
GPR and written to the line buffer and the line buffer is stored back into the data cache. The data cache supports byte writeability to improve the performance of byte and halfword stores. Load hits and store hits can be completed in one clock cycle. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 136 A write miss causes the cache to allocate a new cacheline and update that line—system memory is not updated. Write-back caching can improve system performance by minimizing processor local bus activity. Write-back cachelines are only written to memory during cacheline replacement www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 137: Data-Cache Performance
In general, a data-cache hit completes in one cycle without stalling the processor. The DCU can perform certain cache operations in parallel to improve performance. Combinations of load and store operations—cacheline fills, cacheline flushes, and operations that hit in the March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 138 DCU asserts and deasserts DPP . As is shown in the table, loads from system memory have highest priority and always immediately assert DPP www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 139: Accessing Memory
Memory (collectively, system memory and cache memory) is accessed when instructions are fetched and when a program executes load and store instructions. Other conditions not specified by a program can cause memory accesses to occur, such as cacheline fills and March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 140: Memory Coherency
PowerPC architecture provides the ability to enforce memory-access ordering among multiple programs that share memory. Similar means are provided for programs that share memory with other hardware devices, such as I/O devices. These are: www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 141: Preventing Inappropriate Speculative Accesses
Marking a memory location as guarded does not completely prevent speculative accesses from that memory location. Speculative accesses from guarded storage can occur in the following cases: March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 142 Replacing the mtlr above with tw or twi leaves the LR uninitialized. It would be inappropriate to prefetch from the blr target in this situation. The processor is designed to prevent speculative prefetching when executing the system-trap instructions. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 143: Memory-System Control
The memory-coherency storage attribute controls memory coherency in multiprocessor environments. Because the PPC405x3 core does not provide hardware support for multiprocessor memory coherency, setting or clearing the M storage attribute has no effect. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 144: Storage-Attribute Control Registers
4 GB physical-address space. The five most-significant effective-address bits (EA are used to select a specific bit within the register. Table 5-2 shows the address ranges associated with each register bit. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 145 The DCWR is a privileged SPR with an address of 954 (0x3BA) and can be read and written using the mfspr and mtspr instructions. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 146 Caching Inhibited (I), page 451 for more information. The ICCR is a privileged SPR with an address of 1019 (0x3FB) and can be read and written using the mfspr and mtspr instructions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 147 (as shown in Table 5-2) is accessed using big- endian or little-endian byte ordering. See Byte Ordering, page 349 for more information on big-endian and little-endian memory accesses. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 148: Cache Control
PPC405. These instructions provide the ability to invalidate the entire cache array or a single cacheline, prefetch instructions into the cache, and debug the cache. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 149 PPC405. These instructions provide the ability to invalidate the entire cache array or a single cacheline, prefetch data into the cache, and debug the cache. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 150 EA is calculated using register-indirect with index addressing: EA = (rA|0) + (rB) www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 151: Core-Configuration Register
• Enablement of the U0 storage-attribute exception. • Cache-debug features. Figure 5-13 shows the format of the CCR0. The fields in CCR0 are defined as shown in Table 5-6. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 152 When this bit is set to 1, the processor can prefetch instructions Regions from non-cacheable memory regions into the instruction-prefetch buffers. Clearing this bit to 0 disables prefetching from non- 0—Disabled. cacheable memory regions, generally at a cost to performance. 1—Enabled. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 153 CCR0[IPP] or CCR0[FWOA], both of which affect instruction-cache operation. In this and the following example, registers rN, rM, rX, and rZ are any available GPRs. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 154 ! Turn off MSR[CE,EE] mtmsr rZ ! Synchronize execution. sync ! Modify CCR0. mfspr rN,CCR0 ! Read CCR0 ! Use and/or instructions to modify any CCR0 bits. andi/ori rN,rN,0xnnnn www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 155: Software Management Of Cache Coherency
(0x1000–0x103F). The following program is executed, updating the data words in addresses 0x1004–0x1030: r1,0x1004-4 ! Start at address 0x1004. r2,12 ! Fill 12 words. mtctr r2 ! Initialize counter. r3,0 ! Initialize data to zero. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 156 1030 1030 Coherency Loss Through Dual-Mapping Some memory controllers support dual-mapping of physical-address ranges. With dual- mapping, two address ranges are resolved as a single address range. For example, assume www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 157: Enforcing Coherency With Software
The ending address of shared falls before a cacheline boundary, but that cacheline boundary falls within buffer. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 158 Afterward, software can execute a dccci instruction to invalidate both of these new lines. <Disable interrupts> r1,<start of unused address range as large as data cache> r2,16384 ! Cache size in bytes/2. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 159: Self-Modifying Code
A modifying instruction (or sequence of instructions) is inserted between the instruction load and instruction store. Below is a simple assembler-code sequence that can be used to maintain cache coherency during self-modifying code operations. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 160: Cache Debugging
0—Way A is least-recently used. 1—Way B is least-recently used. The ICDBDR is a privileged, read-only SPR with an address of 979 (0x3D3). It can be read using the mfspr instruction. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 161: Dcread Instruction
0—Cacheline is not valid. 1—Cacheline is valid. 28:30 Reserved Least-Recently Used Contains the LRU bit for the congruence class associated with the cacheline. 0—Way A is least-recently used. 1—Way B is least-recently used. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 162 Chapter 5: Memory-System Management www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 163: Real Mode
Programs reference memory locations using a 32-bit effective address (EA) calculated by the processor based on the address mode (see Effective-Address Calculation, page 344). When real mode is enabled, the March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 164: Virtual Mode
32-Bit Effective Address Effective Page Number Offset 40-Bit Virtual Address Effective Page Number Offset Translation Look-Aside Buffer (TLB) Look-Up 32-Bit Physical Address Real Page Number Offset UG011_37_021302 Figure 6-1: Virtual-Mode Address Translation www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 165 Address Space Process A Process A PID A Process A Process B PID B Process B Process B PID C Process C Process C Process C UG011_39_033101 Figure 6-2: Process-Mapping Example March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 166: Process-Id Register
The unified 64-entry TLB, managed by software, caches a subset of instruction and data page-translation entries accessible by the MMU. Software uses the unified TLB to cache a subset of instruction and data page-translation entries for use by the MMU. Software is www.xilinx.com March 2002 Release 1-800-255-7778...
Page 167: Translation Look-Aside Buffer
UTLB. The ITLB is used to minimize contention between instruction translation and UTLB-update operations. The initialization and management of the ITLB is controlled completely by hardware and is transparent to software. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 168: Tlb Entries
Physical-page identification—These fields identify the translated page in physical memory. • Access control—These fields specify the type of access allowed in the page and are used to protect pages from improper accesses. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 169 WR bit cause a data-storage exception. • ZSEL (Zone select)—TLBLO, bits 24:27. This field selects one of 16 zone fields (Z0– Z15) from the zone-protection register (ZPR). For example, if ZSEL=0b0101, zone field March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 170 ↔ EA 16 KB 0b010 18:21 0:17 0:17 18:31 0:17 ↔ EA 64 KB 0b011 16:21 0:15 0:15 16:31 0:15 ↔ EA 256 KB 0b100 14:21 0:13 0:13 14:31 0:13 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 171: Tlb Access
If access is allowed, the MMU checks the storage-attribute fields to determine how to access the page. The storage-attribute fields specify the caching policy and byte ordering for memory accesses. See Storage-Attribute Fields, page 478, for more information. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 172: Tlb-Access Failures
MMU are disabled. After system software initializes the UTLB with page-translation entries, management of the PPC405 UTLB is usually performed using interrupt handlers running in real mode. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 173 TLB entry was not found in the TLB (shadow and UTLB). Any instruction fetch can cause an instruction TLB-miss exception. See Instruction TLB-Miss Interrupt (0x1200), page 520, for more information. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 174: Virtual-Mode Access Protection
Changing a zone field in the ZPR applies a protection override across all pages in that zone. Without the ZPR, protection changes require individual alterations to each page- translation entry within the zone. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 175: Effect Of Access Protection On Cache-Control Instructions
TLBLO[WR] only. Because this is a privileged instruction, access cannot be denied by zone protection. dcbz—Affected by TLBLO[WR] and (in user mode only) ZPR[Zn]=00. • Other cache-control instructions can invalidate an entire cache-congruence class. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 176 No violation—treated as load. Data-storage interrupt. dcbi Data-storage interrupt. No violation—privileged instruction. dcbst No violation—treated as load. Data-storage interrupt. dcbt No violation—treated as load. No operation. dcbtst No violation—treated as load. No operation. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 177: Utlb Management
If WS=0, the tag portion (TLBHI) is loaded into rD and the PID is updated with the TLBHI[TID] field. If WS=1, the data portion (TLBLO) is loaded into rD. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 178: Recording Page Access And Page Modification
• When pages in physical-memory are replaced to make room for new pages, it is important to know whether the replaced (old) pages were modified. If they were www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 179: Maintaining Shadow-Tlb Consistency
The processor invalidates all shadow-TLB entries when any of the following context-synchronizing events occur: • An isync instruction is executed. • An sc instruction is executed. • An interrupt occurs. • An rfi or rfci instruction is executed. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 180 UTLB. As a general rule, software manipulation of UTLB entries should always be followed by a context-synchronizing operation, typically an isync instruction. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 181: Exceptions And Interrupts
Returning from an interrupt handler to an interrupted program requires that the old machine state and program return address be restored from the save/restore register pair. This is accomplished using a return-from-interrupt instruction. Like interrupts, return-from- interrupt instructions are context synchronizing. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 182: Synchronous And Asynchronous Exceptions
When an interrupt occurs, some software-visible state can be updated to reflect the partial execution of the excepting instruction. The instructions and the effect interrupts have on partial execution are as follows: • Load-multiple and load-string instructions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 183: Ppc405D5 Exceptions And Interrupts
Critical Asynchronous Imprecise External bus error. Data Storage 0x0300 Noncritical Synchronous Precise Data-access violation. Instruction Storage 0x0400 Noncritical Synchronous Precise Instruction-access violation. External 0x0500 Noncritical Asynchronous Precise External noncritical-interrupt signal. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 184: Critical And Noncritical Exceptions
Transferring Control to Interrupt Handlers Figure 7-1 shows how the components of the PPC405 exception mechanism interact when transferring program control to an interrupt handler. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 185 Critical interrupts load SRR2 with the return address. Noncritical interrupts load SRR0 with the return address. Refer to the specific interrupt description in Interrupt Reference, page 502 information on the saved return address. Save the interrupted-program state. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 186: Returning From Interrupt Handlers
(rfci). Both instructions operate in a similar fashion, with the only difference being the save/restore register pair used to restore the interrupted-program state. rfi and rfci perform the following functions: www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 187: Simultaneous Exceptions And Interrupt Priority
(virtual mode only). Instruction storage—Non-executable. Attempted execution of an instruction from a non-executable memory address (virtual mode only). Instruction storage—Guarded. Attempted execution of an instruction from a guarded memory address. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 188: Persistent Exceptions And Interrupt Masking
The following exceptions are persistent and their corresponding interrupts can be disabled: www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 189: Interrupt-Handling Registers
During an interrupt, the contents of the MSR (see page 431) are loaded into either SRR1 (noncritical interrupts) or SRR3 (critical interrupts). Depending on the interrupt, the MSR is updated with the values shown in Table 7-3. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 190 The save/restore registers 0 and 1 (SRR0 and SRR1) are 32-bit registers used to save machine state when a noncritical interrupt occurs. The format of each register is shown in Figure 7-2. 30 31 Interrupted-Instruction Effective Address SRR0 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 191 The instruction that caused the exception. • The instruction that would have executed had no exception occurred. For example, when a watchdog-timer interrupt occurs SRR2 is loaded with the effective address of the next-sequential instruction. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 192: Exception-Vector Prefix Register
ESR register. The fields in the ESR are defined as shown Table 7-5. 10 11 14 15 PIL PPR PTR PEU DST DIZ PFP PAP Figure 7-5: Exception-Syndrome Register (ESR) www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 193 This is true whether or not the other exception occurs simultaneously with the instruction machine-check exception that sets ESR[MCI]. Handling ESR[MCI] in this manner prevents losing a record of an instruction machine- March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 194: Data Exception-Address Register
The conditions that cause the exception for which the interrupt occurs are described. • The methods used to enable and disable (mask) the interrupt are described, if applicable. • The values of the registers affected by taking the interrupt are shown. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 195: Critical-Input Interrupt (0X0100)
Loaded with a copy of the MSR at the point the interrupt occurs. Not used. DEAR [AP, APE, WE, CE, EE, PR, FP, FE0, DWE, DE, FE1, IR, DR] ← 0. [ME] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 196: Machine-Check Interrupt (0X0200)
Determining the cause is dependent on the system implementation. Generally the data machine-check interrupt handler must examine the error-reporting registers located in the external-PLB devices to determine the exception cause. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 197 Loaded with a copy of the MSR at the point the interrupt occurs. Not used. DEAR [AP, APE, WE, CE, EE, PR, FP, ME, FE0, DWE, DE, FE1, IR, DR] ← 0. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 198: Data-Storage Interrupt (0X0300)
Loaded with the effective address of the instruction that caused the data-storage exception. SRR1 Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 199 All remaining bits are cleared to 0. DEAR Loaded with the effective address of the failed data-access. [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 200: Instruction-Storage Interrupt (0X0400)
[MCI] ← Unchanged. All remaining bits are cleared to 0. DEAR Not used. [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 201: External Interrupt (0X0500)
Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 DEAR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 202: Alignment Interrupt (0X0600)
Loaded with the effective address of the operand that caused the alignment exception. [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 203: Program Interrupt (0X0700)
Loaded with the effective address of the instruction that caused the program exception. SRR1 Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 204 [MCI] ← Unchanged. All remaining bits are cleared to 0. DEAR Not used. [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 205: Fpu-Unavailable Interrupt (0X0800)
Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 DEAR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 206: System-Call Interrupt (0X0C00)
Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 DEAR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 207: Apu-Unavailable Interrupt (0X0F20)
Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 DEAR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 208: Programmable-Interval Timer Interrupt (0X1000)
[CE, ME, DE] ← Unchanged. The timer-status register (TSR) is also updated as a result of a PIT exception. Register Value After Exception [PIS] ← 1. All others are unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 209: Fixed-Interval Timer Interrupt (0X1010)
[CE, ME, DE] ← Unchanged. The timer-status register (TSR) is also updated as a result of a FIT exception. Register Value After Exception [FIS] ← 1. All others are unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 210: Watchdog-Timer Interrupt (0X1020)
Loaded with a copy of the MSR at the point the interrupt occurs. Not used. DEAR [AP, APE, WE, CE, EE, PR, FP, FE0, DWE, DE, FE1, IR, DR] ← 0. [ME] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 211: Data Tlb-Miss Interrupt (0X1100)
All remaining bits are cleared to 0. DEAR Loaded with the effective address of the failed data-access. [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 212: Instruction Tlb-Miss Interrupt (0X1200)
Loaded with a copy of the MSR at the point the interrupt occurs. SRR2 Not used. SRR3 DEAR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0. [CE, ME, DE] ← Unchanged. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 213: Debug Interrupt (0X2000)
Chapter 9, Debugging, for more information on debug events. Affected Registers Register Value After Interrupt SRR0 Not used. SRR1 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 214 The debug-status register (DBSR) is also updated as a result of a debug interrupt. See Debug-Status Register, page 541, for more information on the DBSR. Register Value After Interrupt DBSR Updated to reflect the debug event. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 215: Timer Resources
This frequency is determined using external input signals to the processor. Refer to the PPC405 Processor Block Manual for more information on setting the timer frequency. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 216 The TBR number (TBRN) shown in the operand syntax column can be specified as a decimal or hexadecimal value in the assembler listing. Within the instruction opcode, this number is encoded using a split-field notation (see Split-Field Notation, page 571). www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 217: Reading And Writing The Time Base
! Load lower 32-bit time-base value into ry. rz, 0 ! Clear rz. mttbl rz ! Clear TBL to avoid rollover after writing TBU. mttbu rx ! Update TBU. mttbl ry ! Update TBL. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 218: Computing Time Of Day
! Load the number of elapsed seconds. addi rw, rw, 1 ! Add 1 second. rw, posix_sec ! Store the number of elapsed seconds. nochange: rz, posix_ns ! Update elapsed ns. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 219: Timer-Event Registers
In auto-reload mode, the PIT is reloaded with the last value loaded by an mtspr instruction. In this mode, the PIT never contains a value of 0. Auto-reload mode is enabled by setting the auto-reload enable bit in the timer-control register March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 220: Timer-Control Register
01—2 clocks 10—2 clocks 11—2 clocks FIT-Interrupt Enable Enables and disables fixed-interval timer interrupts. 0—Disabled 1—Enabled Auto-Reload Enable Enables and disables the programmable-interval timer auto-reload mode. 0—Disabled 1—Enabled 10:31 Reserved www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 221: Timer-Status Register
0x1020. • Programmable-interval timer (PIT) interrupt. This noncritical interrupt is assigned to exception-vector offset 0x1000. • Fixed-interval timer (FIT) interrupt. This noncritical interrupt is assigned to exception-vector offset 0x1010. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 222: Watchdog-Timer Events
When cleared to 0, the TSR[WIS] bit is not updated or used by the processor. Watchdog time-outs cannot cause an interrupt or reset. The next watchdog time- out sets this bit to 1. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 223 If no errors occur, software must periodically update the state of the state machine to prevent a reset. Figure 8-6, shows three possible methods for properly managing the state machine: • Method (1)—an interrupt handler manages the state machine. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 224: Programmable-Interval Timer Events
PIT interrupt is pending. A PIT interrupt occurs if the status bit is set and the interrupt is enabled. PIT events are disabled as follows: • Disable PIT interrupts by clearing TCR[PIE]=0. • Clear TSR[PIS] to 0 to remove pending PIT interrupts. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 225: Fixed-Interval Timer Events
A FIT interrupt occurs if the status bit is set and the interrupt is enabled. To disable FIT interrupts, software must clear TCR[FIE]=0. TSR[FIS] should be cleared to 0 to remove pending FIT interrupts. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 226 Chapter 8: Timer Resources www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 227 Exception Status—Indicates the status of pending synchronous exceptions. Most Recent Reset—Indicates the cause of the most-recent reset. • A debug interface (JTAG) and a trace interface for connecting external hardware and software debug tools. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 228: Debug Modes
The handler can be used to collect processor-status information and to alter software-visible resources. An external debug event can cause a debug interrupt only when both DBCR0[IDM]=1 and MSR[DE]=1. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 229: Debug Registers
• Debug-status register (DBSR). • Instruction address-compare registers (IAC1–IAC4). • Data address-compare registers (DAC1–DAC2). • Data value-compare registers (DVC1–DVC2). A description of each register is provided in the following sections. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 230: Debug-Control Registers
1 (IAC1) debug event is enabled. 0—Disabled 1—Enabled Instruction Address-Compare 2 Debug Event Specifies whether or not the instruction address- compare 2 (IAC2) debug event is enabled. 0—Disabled 1—Enabled www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 231 Table 9-2. 10 11 12 13 14 15 16 19 20 D1R D2R D1W D2W DA12 DA12X DV1M DV2M DV1BE DV2BE Figure 9-2: Debug-Control Register 1 (DBCR1) March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 232 (DVC2 event). The comparison is made using 01—All selected bytes must match the bytes selected by DV2BE. 10—At least one selected byte must match 11—At least one selected halfword must match www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 233: Debug-Status Register
Unconditional Debug Event Indicates whether an unconditional debug event occurred. 0—Did not occur 1—Occurred Instruction-Address Compare 1 Debug Event Indicates whether an IAC1 debug event occurred. 0—Did not occur 1—Occurred March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 234: Instruction Address-Compare Registers
IAC2, IAC3, and IAC4. These registers are used by the instruction address- compare debug event. Figure 9-4 shows the format of the IACn registers. The instruction effective-addresses loaded in these registers must be word aligned (address bits 30:31 must be 0). www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 235: Debug Events
DBCR1). Some of the debug events make use of one or more of the compare registers (IACn, DACn, and DVCn). Depending on the debug mode, a debug event causes the following to occur: March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 236 Table 9-4 summarizes the debug resources used by each debug event. Table 9-4: Debug Resources Used by Debug Events Debug Event DBCR0 DBCR1 DBSR Instruction Complete Branch Taken Exception Taken www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 237: Instruction-Complete Debug Event
If debug interrupts are enabled, the SRR2 register is loaded with the effective address of the instruction following the one that caused the IC event. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 238: Branch-Taken Debug Event
TDE debug event by setting the TDE bit in the debug-status register (DBSR[TDE]) to 1. After a TDE event is recorded by a debugger, the status bit should be cleared to prevent ambiguity when recording future debug events. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 239: Unconditional Debug Event
IAC address-range comparisons must be disabled as follows: • DBCR0[IA12]=0 for IAC1 and IAC2 exact-match comparisons. • DBCR0[IA34]=0 for IAC3 and IAC4 exact-match comparisons. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 240 If DBCR0[IA34X]=0, instruction addresses from (IAC3) to (IAC4)-1 fall within the range. Addresses from 0 to (IAC3)-1 and (IAC4) to 0xFFFF_FFFF fall outside the range. • When set, the corresponding range is exclusive. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 241: Data Address-Compare Debug Event
DACn registers. Aligned memory accesses generate a single effective address that is used in checking for a DAC event. Unaligned memory accesses, load/store multiple instructions, and load/store March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 242 DAC2 register. This field specifies which low-order address bits are ignored during the comparison. Because low-order address bits are ignored, the comparison is aligned on an address boundary equivalent to the www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 243 D1R and/or D2R bits in the DBCR1 register. Only one of the two bits must be set to enable read checking for the entire range. If March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 244 DAC events can be caused by the execution of cache-control instructions. The following summarizes the type of DAC events that can occur when a cache- control instruction is executed: • Cache-control instructions that can modify data are treated as stores www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 245: Data Value-Compare Debug Event
A DAC match occurs. The operand effective-address of the data-access instruction must match the value contained in one of the DACn registers, using the conditions specified by the DBCR1 register. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 246 Here, a DVC event occurs if either the upper halfword or lower halfword of the DVCn register matches the corresponding operand halfword. Table 9-11 shows example settings of DV1BE and DV1M and how they affect detection of a DVC1 match. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 247 DVC events are enabled but fail to occur. After a DAC or DVC event is recorded by a debugger, the corresponding status bits should be cleared to prevent ambiguity when recording future debug events. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 248: Imprecise Debug Event
All bits in the DBSR except for the most-recent reset (MRR) must be cleared to 0 to restart the timers. The timers are unfrozen when the processor recognizes the cleared state of the DBSR. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 249: Debug Interface
9-13. At the board level, the connector should be placed as close as possible to the processor chip to ensure signal integrity. Position 14 is used as a connection key and does not contain a pin. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 250 (1KΩ or less) should be used to provide short-circuit current-limiting protection. A 10KΩ pull-up resistor must be connected to these signals to ensure proper chip operation when these inputs are not used. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 251 BSDL. This standard is a supplement to IEEE standards 1149.1-1990 (standard test-access port) and 1149.1a-1993 (boundary-scan architecture). BSDL is a subset of the VHSIC hardware description language (VHDL), a standard defined by IEEE 1076-1993. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 252 March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 253: Reset And Initialization
Processor State After Reset System software is responsible for fully initializing and configuring most processor resources. After a reset, the contents of most PPC405 registers are undefined and software March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 254 Special-Purpose Registers Table 10-2 shows the contents of the special-purpose registers (SPRs) that have defined values following a reset. The contents of all other SPRs are undefined after a reset. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 255: First Instruction
Configure the real-mode memory system by updating the storage- attribute control registers. After reset, all memory is marked as guarded storage, preventing speculative instruction fetches. To improve fetch performance, the March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 256 The timer resources must be initialized. If timers are not used, the TCR register must be initialized to prevent the occurrence of timer exceptions. Timer exceptions are enabled when critical and noncritical external exceptions are enabled. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 257: Sample Initialization Code
/* -------------------------------------------------------- /* Invalidate the instruction cache and enable cachability. /* -------------------------------------------------------- iccci; /* Flash invalidate the cache. */ mtspr(ICCR, i_cache_cachability); /* Enable the instruction cache */ March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 258 /* These can be initialized by the operating system. */ /* ------------------------------------------------------ */ /* If enabling translation, the TLB must be initialized. */ /* Set the machine state as desired. */ mtmsr(machine_state); www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 259 /* Initialize other processor resources. */ /* ------------------------------------- */ /* ----------------------------------- */ /* Initialize non-processor resources. */ /* ----------------------------------- */ /* ----------------------------------------------- */ /* Branch to operating system or application code. */ /* ----------------------------------------------- */ March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 260 March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 261: Instruction Set
(e.g. add). Name—The descriptive name for the instruction. For example, the descriptive name for the srawi instruction is Shift Right Algebraic Word Immediate. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 262: Instruction Encoding
0. If any bit in a reserved field does not contain 0, the instruction form is invalid and its result is undefined. Unless otherwise noted, invalid instruction forms execute without causing an illegal- instruction exception. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 263: Split-Field Notation
SPRN, DCRN, and TBRN values. The assembler handles the conversion to the split-field format when encoding the instruction. Alphabetical Instruction Listing The following pages list the instructions supported by the PPC405 in alphabetical order. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 264 If an overflow occurs, it is possible that the contents of CR0 do not reflect the infinitely precise result. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 265 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 266 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 267 (rD) rA |0) + EXTS(SIMM) Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 268 ← else XER[CA] Registers Altered • • XER[CA]. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 269 • XER[CA]. • CR[CR0] LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 270 ) ← ( rA |0) + (SIMM || Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 271 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 272 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 273 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 274 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 275 Registers Altered • • CR[CR0] LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 276 Registers Altered • • CR[CR0] LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 277 CIA + 4 Registers Altered • LR if LK=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 278 0b00) ← else NIA CIA + EXTS(BD 0b00) ← else NIA CIA + 4 = 1 then if LK ← (LR) CIA + 4 Registers Altered • CTR if BO www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 279 Alphabetical Instruction Listing • LR if LK=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 280 • Reserved bits containing a non-zero value. =0. In this case the branch is taken if the branch condition is true. The contents of • www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 281 Alphabetical Instruction Listing the decremented CTR are used as the NIA. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 282 LR if LK=1. Exceptions • None. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 283 Alphabetical Instruction Listing Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 284 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 285 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 286 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 287 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 288 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 289 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 290 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 291 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 292 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 293 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 294 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 295 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 296 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 297 Pseudocode ← rA |0) + ( rB ) Allocate data cacheline corresponding to EA Registers Altered • None. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 298 This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. Implementation of this instruction is optional, and it is not guaranteed to be implemented on all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 299 Debug exceptions can occur as a result of executing this instruction. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 300 Chapter 11: Instruction Set Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 301 This instruction is considered a “store” with respect to the above data-access exceptions. It is also considered a “store” with respect to data address-compare (DAC) debug exceptions. Debug exceptions can occur as a result of executing this instruction. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 302 Reserved bits containing a non-zero value. Compatibility This instruction is defined by the operating-environment architecture level (OEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 303 Debug exceptions can occur as a result of executing this instruction. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 304 Chapter 11: Instruction Set Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 305 (DAC) debug exceptions. Debug exceptions can occur as a result of executing this instruction. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 306 Chapter 11: Instruction Set Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 307 (DAC) debug exceptions. Debug exceptions can occur as a result of executing this instruction. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 308 Chapter 11: Instruction Set Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 309 Alignment—if the EA is marked as non-cachable or write-through. The alignment exception handler can emulate the effect of this instruction by storing zeros to the corresponding block of main memory. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 310 Reserved bits containing a non-zero value. Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 311 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. • Program—Attempted execution of this instruction from user mode. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 312 • Reserved bits containing a non-zero value. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 313 19:25 Reserved Dirty Contains a copy of the cache-line dirty bit indicating whether or not the line contains modified data. 0—Cacheline is not dirty. 1—Cacheline is dirty. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 314 • Reserved bits containing a non-zero value. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 315 Pseudocode rD ) ← ( rA ) ÷ ( rB ) Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO • XER[OV, SO] if OE=1. Exceptions • None. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 316 Chapter 11: Instruction Set Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 317 LT, GT, EQ, SO • XER[OV, SO] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 318 Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture and the PowerPC embedded-environment architecture. The instruction is not part of the PowerPC Book-E architecture. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 319 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 320 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 321 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 322 TLB- miss exceptions. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 323 Alphabetical Instruction Listing Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 324 TLB- miss exceptions. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 325 This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC embedded-environment architecture and the PowerPC Book-E architecture. It is not defined by the PowerPC architecture, and is therefore not implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 326 • Reserved bits containing a non-zero value. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 327 If an instruction word is loaded it is specified using CCR0[CIS]=0—Instruction effective-address bits EA . CCR0[CIS] controls the type of word. 27:29 information loaded into this field. CCR0[CIS]=1—Instruction tag. 22:26 Reserved March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 328 • Reserved bits containing a non-zero value. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 329 Reserved bits containing a non-zero value. Compatibility This instruction is defined by the virtual-environment architecture level (VEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 330 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 331 • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 332 • Reserved bits containing a non-zero value. • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 333 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 334 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 335 • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 336 • Reserved bits containing a non-zero value. • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 337 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 338 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 339 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 340 • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 341 • Reserved bits containing a non-zero value. • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 342 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 343 • rA is in the range of registers to be loaded, including the case rA=rD=0. The word that would have been loaded into rA is discarded. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 344 Chapter 11: Instruction Set Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 345 (GPR(reg)) ≠ rA ∨ if ((reg (reg FINAL ← then (GPR(reg) MS(EA,1) bit:bit+7 ← bit + 8 = 32 if bit ← then bit ← EA + 1 − ← March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 346 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 347 ← then reg ≠ rA ∨ if ((reg (reg FINAL ← then (GPR(reg)) ≠ rA ∨ if ((reg (reg FINAL ← then (GPR(reg) MS(EA,1) bit:bit+7 ← bit + 8 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 348 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 349 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 350 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 351 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 352 • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 353 • Reserved bits containing a non-zero value. • rA=rD. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 354 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 355 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 356 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 357 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 358 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 359 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 360 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 361 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 362 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 363 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 364 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 365 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 366 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 367 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 368 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 369 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 370 PowerPC Book-E architecture. It is not defined by the PowerPC architecture, and is therefore not implemented by all PowerPC processors. The specific registers accessed by this instruction are implementation dependent. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 371 This instruction is defined by the operating-environment architecture level (OEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 372 PowerPC Book-E architecture. It is part of the user instruction-set architecture (UISA) and the operating-environment architecture (OEA). It is implemented by all PowerPC processors. However, not all SPRs supported by the PPC405 are supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 373 PowerPC Book-E architecture does not support this instruction, but does support the time- base registers. Software running on PowerPC Book-E processors must use the mfspr instruction to access the time-base registers. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 374 Simplified mnemonics defined for this instruction are described in Other Simplified Mnemonics, page 834. Pseudocode ← mask (CRM (CRM (CRM (CRM ← ∧ ∨ ∧ ¬ (CR) ((rS) mask) ((CR) mask) Registers Altered • www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 375 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 376 PowerPC Book-E architecture. It is not defined by the PowerPC architecture, and is therefore not implemented by all PowerPC processors. The specific registers accessed by this instruction are implementation dependent. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 377 This instruction is defined by the operating-environment architecture level (OEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 378 PowerPC Book-E architecture. It is part of the user instruction-set architecture (UISA) and the operating-environment architecture (OEA). It is implemented by all PowerPC processors. However, not all SPRs supported by the PPC405 are supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 379 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 380 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 381 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 382 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 383 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 384 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 385 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 386 Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 387 ← rD ) prod 16:47 Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 388 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 389 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 390 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 391 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 392 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 393 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 394 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 395 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 396 Rc=1. LT, GT, EQ, SO • XER[SO, OV] if OE=1 Exceptions • None. Compatibility This instruction is implementation specific and is not guaranteed to be supported by other PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 397 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 398 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 399 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 400 ) (rS) 0 || UIMM) Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 401 ∨ rA ) (rS) (UIMM Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 402 This instruction is defined by the operating-environment architecture level (OEA) of the the PowerPC embedded-environment architecture and the PowerPC Book-E architecture. It is not defined by the PowerPC architecture, and is therefore not implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 403 This instruction is defined by the operating-environment architecture level (OEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 404 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 405 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 406 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 407 This instruction is defined by the PowerPC architecture, the PowerPC embedded- environment architecture, and the PowerPC Book-E architecture. It is part of the user instruction-set architecture (UISA) and the operating-environment architecture (OEA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 408 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 409 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 410 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 411 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 412 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 413 Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 414 • Reserved bits containing a non-zero value. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 415 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 416 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 417 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 418 Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 419 • Reserved bits containing a non-zero value. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 420 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 421 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 422 ← then i ← EA + 1 − ← Registers Altered • None. Exceptions • Data storage—if the access is prevented by zone protection when data relocation is enabled. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 423 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 424 ← then r ← MS(EA, 1) (GPR(r) i:i+7 ← i + 8 = 32 if i ← then i ← EA + 1 − ← Registers Altered • None. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 425 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 426 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 427 EA is not found in the TLB. Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • Reserved bits containing a non-zero value. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 428 Chapter 11: Instruction Set Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 429 (rS) ← RESERVE ← (CR[CR0]) 0b00 else ← (CR[CR0]) 0b00 Registers Altered • CR[CR0] LT, GT, EQ, SO Exceptions • Alignment—if the EA is not aligned on a word boundary. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 430 Data TLB miss—if data relocation is enabled and a valid translation-entry corresponding to the EA is not found in the TLB. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 431 Execution of any of the following invalid-instruction forms results in a boundedly- undefined result rather than a program exception: • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 432 • Reserved bits containing a non-zero value. • rA=0. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 433 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 434 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 435 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 436 LT, GT, EQ, SO • XER[SO, OV] if OE=1. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 437 ← else XER[CA] Registers Altered • • XER[CA]. Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 438 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 439 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 440 • Reserved bits containing a non-zero value. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 441 This instruction is defined as optional by the operating-environment architecture level (OEA) of the PowerPC architecture and the PowerPC embedded-environment architecture. Because it is optional it is not implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 442 Reserved bits containing a non-zero value. • WS value greater than 1. Compatibility This instruction is defined as optional by the operating-environment architecture level (OEA) of the PowerPC embedded-environment architecture and the PowerPC Book-E www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 443 Alphabetical Instruction Listing architecture. Because it is optional and not defined by the PowerPC architecture it is not implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 444 ← else (rD) Undefined if Rc ← then CR[CR0] Registers Altered • • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • Program—Attempted execution of this instruction from user mode. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 445 (OEA) of the PowerPC embedded-environment architecture and the PowerPC Book-E architecture. Because it is optional and not defined by the PowerPC architecture it is not implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 446 This instruction is defined as optional by the operating-environment architecture level (OEA) of the PowerPC architecture, the PowerPC embedded-environment architecture, and the PowerPC Book-E architecture. Because it is optional it is not implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 447 Reserved bits containing a non-zero value. • WS value greater than 1. Compatibility This instruction is defined as optional by the operating-environment architecture level (OEA) of the PowerPC embedded-environment architecture and the PowerPC Book-E March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 448 Chapter 11: Instruction Set architecture. Because it is optional and not defined by the PowerPC architecture it is not implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 449 > rB )) ∧ = 1) then trap rA ) rB )) ∧ = 1) then trap rA ) < rB )) ∧ = 1) then trap rA ) > March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 450 This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. However, the behavior of the trap as it relates to the debug exception is implementation-specific. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 451 ) EXTS(SIMM)) > ∧ = 1) then trap rA ) EXTS(SIMM)) ∧ = 1) then trap rA ) EXTS(SIMM)) < ∧ = 1) then trap rA ) EXTS(SIMM)) > March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 452 This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. However, the behavior of the trap as it relates to the debug exception is implementation-specific. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 453 This instruction is defined by the operating-environment architecture level (OEA) of the the PowerPC embedded-environment architecture and the PowerPC Book-E architecture. Because it is not defined by the PowerPC architecture it is not implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 454 This instruction is defined by the operating-environment architecture level (OEA) of the the PowerPC embedded-environment architecture and the PowerPC Book-E architecture. Because it is not defined by the PowerPC architecture it is not implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 455 • CR[CR0] if Rc=1. LT, GT, EQ, SO Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 456 ) ← (rS) ⊕ ( 0 || UIMM) Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 457 ) ← (rS) ⊕ (UIMM || Registers Altered • Exceptions • None. Compatibility This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is implemented by all PowerPC processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 458 Chapter 11: Instruction Set www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 459: Register Summary
Data Exception-Address Register, page 502 DVC1 Data Value-Compare 1 Data Value-Compare Registers, page 543 DVC2 Data Value-Compare 2 Exception-Syndrome Register Exception-Syndrome Register, page 500 EVPR Exception-Vector Prefix Register Exception-Vector Prefix Register, page 500 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 460: General-Purpose Registers
General-Purpose Registers Table A-2 lists the general-purpose registers (GPRs). A binary version of the register number is shown to assist in interpreting instruction encodings often found in machine- code listings. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 461 General-Purpose Register 27 0x1C 0b11100 Read/Write Undefined General-Purpose Register 28 0x1D 0b11101 Read/Write Undefined General-Purpose Register 29 0x1E 0b11110 Read/Write Undefined General-Purpose Register 30 0x1F 0b11111 Read/Write Undefined General-Purpose Register 31 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 462: Machine-State Register And Condition Register
0x0000_0000 EVPR Exception-Vector Prefix Register 0x3D6 0x2DE 0b10110_11110 Read/Write Undefined IAC1 Instruction Address-Compare 1 1012 0x3F4 0x29F 0b10100_11111 Read/Write Undefined IAC2 Instruction Address-Compare 2 1013 0x3F5 0x2B5 0b10101_11111 Read/Write Undefined www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 463 Table A-5 lists the special-purpose registers sorted by the SPRN. The SPRN is the SPR number that appears in the assembler syntax. This table is useful in interpreting assembler listings. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 464 0x3BD 0x3BD 0b11101_11101 Read/Write 0x0000_0000 ICDBDR Instruction-Cache Debug-Data Register 0x3D3 0x27E 0b10011_11110 Read-Only Undefined Exception-Syndrome Register 0x3D4 0x29E 0b10100_11110 Read/Write 0x0000_0000 DEAR Data-Error Address Register 0x3D5 0x2BE 0b10101_11110 Read/Write Undefined www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 465 SPRG2 SPR General-Purpose Register 2 0x112 0x248 0b10010_01000 Read/Write Undefined DBCR0 Debug-Control Register 0 1010 0x3F2 0x25F 0b10010_11111 Read/Write 0x0000_0000 SPRG3 SPR General-Purpose Register 3 0x113 0x268 0b10011_01000 Read/Write Undefined March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 466 0x3BD 0x3BD 0b11101_11101 Read/Write 0x0000_0000 SRR2 Save/Restore Register 2 0x3DE 0x3DE 0b11110_11110 Read/Write Undefined Processor-Version Register 0x11F 0x3E8 0b11111_01000 Read-Only 0x2001_0820 SRR3 Save/Restore Register 3 0x3DF 0x3FE 0b11111_11110 Read/Write Undefined www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 467: Time-Base Registers
PPC405 processor but on the same chip. Although the PPC405 does not contain DCRs, the mfdcr and mtdcr instructions are used by privileged software to access their contents. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 468 Appendix A: Register Summary www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 469: Instruction Summary
SIMM addis SIMM addme 00000 addze 00000 andc andi. UIMM andis. UIMM AA LK AA LK bcctr 00000 bclr 00000 crfD cmpi crfD SIMM cmpl crfD cmpli crfD SIMM March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 470 00000 00000 00000 extsb 00000 extsh 00000 icbi 00000 icbt 00000 iccci 00000 icread 00000 isync 00000 00000 00000 lbzu lbzux lbzx lhau lhaux lhax lhbrx www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 471 00000 mcrxr crfD 00000 00000 mfcr 00000 00000 mfdcr DCRF mfmsr 00000 00000 mfspr SPRF mftb TBRF mtcrf mtdcr DCRF mtmsr 00000 00000 mtspr SPRF mulchw mulchwu March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 472 UIMM oris UIMM rfci 00000 00000 00000 00000 00000 00000 rlwimi rlwinm rlwnm 00000 00000 00000 00000 0000 sraw srawi stbu stbux stbx sthbrx sthu www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 473: Instructions Sorted By Opcode
00000 00000 wrteei 00000 00000 0000 xori UIMM xoris UIMM Instructions Sorted by Opcode Table B-2 lists the PPC405 instruction set in numeric order by primary and secondary opcode. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 474 SIMM subfic SIMM cmpli crfD SIMM cmpi crfD SIMM addic SIMM addic. SIMM addi SIMM addis SIMM AA LK 00000 00000 00000 00000 0000 AA LK mcrf crfD crfS 00000 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 475 UIMM oris UIMM xori UIMM xoris UIMM andi. UIMM andis. UIMM crfD subfc addc mulhwu mfcr 00000 00000 lwarx lwzx cntlzw 00000 cmpl crfD subf dcbst 00000 lwzux andc March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 476 00000 stbx subfme 00000 addme 00000 mullw dcbtst 00000 stbux icbt 00000 dcbt 00000 lhzx lhzux mfdcr DCRF mfspr SPRF lhax tlbia 00000 00000 00000 mftb TBRF lhaux sthx www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 477 00000 lhbrx sraw srawi eieio 00000 00000 00000 tlbsx sthbrx extsh 00000 tlbre extsb 00000 iccci 00000 tlbwe icbi 00000 icread 00000 dcbz 00000 1014 lwzu March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 478: Instructions Grouped By Function
Table B-3: Integer Add and Subtract Instructions 21 22 addc adde addi SIMM addic SIMM addic. SIMM addis SIMM addme 00000 addze 00000 00000 subf subfc subfe subfic SIMM subfme 00000 subfze 00000 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 479 SIMM mullw Table B-5: Integer Multiply-Accumulate Instructions 21 22 macchw macchws macchwsu macchwu machhw machhws machhwsu machhwu maclhw maclhws maclhwsu maclhwu nmacchw nmacchws nmachhw nmachhws nmaclhw nmaclhws March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 480 UIMM andis. UIMM cntlzw 00000 extsb 00000 extsh 00000 nand UIMM oris UIMM xori UIMM xoris UIMM Table B-8: Integer Rotate Instructions rlwimi rlwinm rlwnm Table B-9: Integer Shift Instructions www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 481 Table B-10: Integer Load Instructions lbzu lbzux lbzx lhau lhaux lhax lhzu lhzux lhzx lwzu lwzux lwzx Table B-11: Integer Store Instructions stbu stbux stbx sthu sthux sthx stwu stwux stwx March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 482 00000 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 483 00000 00000 mfcr 00000 00000 mfdcr DCRF mfmsr 00000 00000 mfspr SPRF mftb TBRF mtcrf mtdcr DCRF mtmsr 00000 00000 mtspr SPRF wrtee 00000 00000 wrteei 00000 00000 0000 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 484: Instructions Grouped By Form
Table B-23: B Form 30 31 AA LK Table B-24: D Form SIMM mulli SIMM subfic SIMM cmpli crfD SIMM www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 485 UIMM xoris UIMM andi. UIMM andis. UIMM lwzu lbzu stwu stbu lhzu lhau sthu stmw Table B-25: I Form 30 31 AA LK Table B-26: M Form rlwimi rlwinm rlwnm March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 486 00000 lwzux andc mfmsr 00000 00000 dcbf 00000 lbzx lbzux wrtee 00000 00000 mtmsr 00000 00000 stwcx. stwx wrteei 00000 00000 0000 stwux stbx dcbtst 00000 stbux icbt 00000 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 487 00000 00000 00000 lswi sync 00000 00000 00000 stswx stwbrx stswi dcba 00000 lhbrx sraw srawi eieio 00000 00000 00000 tlbsx sthbrx extsh 00000 tlbre extsb 00000 iccci 00000 tlbwe March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 488 00000 Table B-31: XO Form 21 22 machhwu machhw nmachhw machhwsu machhws www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 489: Instruction Set Information
Table B-32 classifies general information about the PPC405 instruction set. A lower-case “x” within a cell indicates the instruction is a member of the class specified by the column heading. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 490 UISA cmpi UISA UISA cmpl cmpli UISA cntlzw UISA crand UISA UISA crandc creqv UISA UISA crnand crnor UISA UISA cror crorc UISA UISA crxor dcba dcbf dcbi dcbst dcbt www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 491 UISA lhau UISA lhaux UISA UISA lhax lhbrx UISA UISA lhzu UISA lhzux UISA lhzx UISA UISA lswi UISA lswx UISA lwarx UISA UISA lwbrx UISA lwzu UISA lwzux UISA March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 492 UISA mfspr mftb mtcrf UISA mtdcr mtmsr UISA mtspr mulchw UISA mulchwu UISA mulhhw UISA mulhhwu UISA mulhw UISA mulhwu UISA UISA mullhw mullhwu UISA mulli UISA mullw UISA www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 493 UISA UISA sraw UISA srawi UISA UISA UISA stbu UISA stbux UISA stbx UISA UISA sthbrx UISA sthu UISA sthux UISA sthx UISA UISA stmw stswi UISA stswx UISA UISA March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 494: List Of Mnemonics And Simplified Mnemonics
If the mnemonic is a simplified mnemonic, its equivalent mnemonic is listed in the column headed “Equivalent Mnemonic”. Otherwise, the column is shaded gray. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 495 AND with Complement and Record andc. andi. AND Immediate and Record page 583 andis. AND Immediate Shifted and Record page 584 Branch page 585 Branch Absolute Branch Conditional page 586 Branch Conditional Absolute March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 496 Branch if Decremented CTR Zero and Condition False to Link Register and Link bclrl page 824 bdzl Branch if Decremented CTR Zero and Link page 823 bdzla Branch if Decremented CTR Zero Absolute and Link bcla page 823 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 497 Branch if Greater Than Absolute page 825 bgtctr Branch if Greater Than to Count Register bcctr page 826 bgtctrl Branch if Greater Than to Count Register and Link bcctrl page 827 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 498 Branch if Not Greater Than Absolute page 825 bngctr Branch if Not Greater Than to Count Register bcctr page 826 bngctrl Branch if Not Greater Than to Count Register and Link bcctrl page 827 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 499 Branch if Condition True Absolute and Link bcla page 823 btlr Branch if Condition True to Link Register bclr page 823 btlrl Branch if Condition True to Link Register and Link bclrl page 824 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 500 Data Cache Block Touch page 613 dcbtst Data Cache Block Touch for Store page 615 dcbz Data Cache Block Clear to Zero page 617 dccci Data Cache Congruence Class Invalidate page 619 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 501 Load Byte and Zero with Update Indexed page 640 lbzx Load Byte and Zero Indexed page 641 Load Halfword Algebraic page 642 lhau Load Halfword Algebraic with Update page 643 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 502 Multiply Accumulate Cross Halfword to Word Modulo Unsigned and Record macchwuo Multiply Accumulate Cross Halfword to Word Modulo Unsigned with Overflow Enabled macchwuo. Multiply Accumulate Cross Halfword to Word Modulo Unsigned with Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 503 Multiply Accumulate Low Halfword to Word Modulo Unsigned and Record maclhwuo Multiply Accumulate Low Halfword to Word Modulo Unsigned with Overflow Enabled maclhwuo. Multiply Accumulate Low Halfword to Word Modulo Unsigned with Overflow Enabled and Record March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 504 Move From Programmable-Interval Timer mfpvr Move From Processor-Version Register mfsgr Move From Storage Guarded Register mfsler Move From Storage Little-Endian Register mfspr Move from Special Purpose Register page 680 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 505 Move to Debug-Control Register 0 mtdbcr1 Move to Debug-Control Register 1 mtdbsr Move to Debug-Status Register mtdccr Move to Data-Cache Cachability Register mtdcr Move to Device Control Register page 684 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 506 Move to Save/Restore Register 2 mtsrr3 Move to Save/Restore Register 3 mtsu0r Move to Storage User-Defined 0 Register mttbl Move to Time-Base Lower mtspr page 830 mttbu Move to Time-Base Upper www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 507 Multiply Low Word with Overflow Enabled and Record nand NAND page 697 nand. NAND and Record Negate page 698 neg. Negate and Record nego Negate with Overflow Enabled nego. Negate with Overflow Enabled and Record March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 508 Negative Multiply Accumulate Low Halfword to Word Saturate Signed with Overflow Enabled and Record No operation page 834 page 705 NOR and Record nor. Complement (Not) Register page 835 not. Complement (Not) Register and Record nor. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 509 Shift Right Immediate rlwinm page 829 srwi. Shift Right Immediate and Record rlwinm. Store Byte page 720 stbu Store Byte with Update page 721 stbux Store Byte with Update Indexed page 722 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 510 746 subfme. Subtract from Minus One Extended and Record subfmeo Subtract from Minus One Extended with Overflow Enabled subfmeo. Subtract from Minus One Extended with Overflow Enabled and Record www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 511 Trap if Greater Than or Equal twgei Trap if Greater Than or Equal Immediate twgt Trap if Greater Than twgti Trap if Greater Than Immediate Trap Word Immediate page 759 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 512 Write External Enable page 761 wrteei Write External Enable Immediate page 762 page 763 xor. XOR and Record xori XOR Immediate page 764 xoris XOR Immediate Shifted page 765 www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 513: Simplified Mnemonics
The detailed instruction syntax for the simplified mnemonics listed in Table C-2 are shown Table C-3 through Table C-6. A cross-reference to the appropriate table is shown in the column heading of Table C-2. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 514 Branch if CTR = 0 and Condition True (CR Decrement CTR, bdzf b, target bc 2, b, target bdzfa b, target bca 2, b, target Branch if CTR = 0 and Condition False (CR www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 515 Branch if CTR = 0 Decrement CTR, bdztl b, target bcl 10, b, target bdztla b, target bcla 10, b, target Branch if CTR = 0 and Condition True (CR March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 516: Comparison Conditional Branches
The remaining fields are abbreviated as shown in Table C-1, page 821. Table C-7: Abbreviations for Comparison Conditional Branches Abbreviation Description Less than Less than or equal Equal www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 517 4, 4×n+1, target blea n, target bca 4, 4×n+1, target Branch if Equal beq n, target bc 12, 4×n+2, target beqa n, target bca 12, 4×n+2, target March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 518 12, 4×n+0, target bltla n, target bcla 12, 4×n+0, target Branch if Less Than or Equal blel n, target bcl 4, 4×n+1, target blela n, target bcla 4, 4×n+1, target www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 519: Branch Prediction
A conditional branch with a non-negative displacement field is predicted not taken (fall through). • A conditional branch to an address in the LR or CTR is predicted not taken (fall through). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 520: Compare Instructions
The variables bx and by are used to specify individual CR bits. Table C-14: Simplified Mnemonics for CR-Logical Instructions Operation Simplified Mnemonic Equivalent Mnemonic Condition Register Set crset bx creqv bx, bx, bx www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 521: Rotate And Shift Instructions
0, 31−n srwi rA, rS, n (n < 32) Shift Right Immediate rlwinm rA, rS, 32−n, n, 31 srwi. rA, rS, n (n < 32) rlwinm. rA, rS, 32−n, n, 31 March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 522 1019 Instruction-Cache Debug-Data Register — — mficdbdr rD mfspr rD, 979 Link Register mtlr rS mtspr 8, rS mflr rD mfspr rD, 8 Notes: Performs a clear to zero operation. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 523: Subtract Instructions
The subtract-from instructions subtract the second operand (rA) from the third operand (rB). The simplified mnemonics in Table C-17 use the order in which the third operand is subtracted from the second operand. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 524: Tlb-Management Instructions
In this table, the column headed “<U” indicates an unsigned less-than comparison and the column headed “>U” indicates an unsigned greater-than comparison www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 525 Trap if logically not greater than twlng rA, rB tw 6, rA, rB twlngi rA, SIMM twi 6, rA, SIMM Trap if unconditional trap tw 31, rA, rB twi 31, rA, SIMM — March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 526: Other Simplified Mnemonics
Complement Register The simplified mnemonics in Table C-25 provide a shorthand for complementing the contents of a GPR. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 527: Move To Condition Register
GPR into the CR. Table C-26: Simplified Mnemonic for Move to Condition Register Operation Simplified Mnemonic Equivalent Mnemonic Move to Condition Register mtcr rS mtcrf 0xFF, rS March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 528 Appendix C: Simplified Mnemonics www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 529: Programming Considerations
The examples show a conditional sequence that begins with an lwarx instruction. This can be followed by memory accesses and/or computations on the loaded value. The sequence ends with a March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 530 CR0[EQ] according to whether the value loaded is zero. This example assumes that the address of the memory word is in r3, the new (nonzero) data is stored from r4, and the old data is loaded into r5. www.xilinx.com March 2002 Release 1-800-255-7778...
Page 531: Compare And Swap
This synchronizes program context. The sync instruction could be used but performance would be degraded because the sync instruction waits for all outstanding memory accesses to complete with respect to other processors. This is not required by the procedure. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 532: List Insertion
0–31. When − − n > 2, the number of instructions required is 2n 1 (immediate shifts) or 3n 1 (non- www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 533 Shift-right algebraic immediate, n = 3 (shift amount < 32) • March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 534: Code Optimization Guidelines
(Var28 || Var29 || Var30 || Var 31) branch to target The above pseudocode can be implemented in assembler using branches as follows: bt 28, target bt 29, target bt 30, target bt 31, target www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 535: Cache Usage
Code and data can be accessed much faster if it is located in the processor caches instead of external memory. Code and data can be organized to minimize cache misses, reducing the need for external memory accesses. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 536: Instruction Performance
The execution time of branches on the PPC405 can be determined as follows: • A known not taken branch does not have condition dependencies (they are resolved) or www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 537 Otherwise, the latency cycle numbers apply. A multiply or MAC instruction can follow another multiply or MAC and still meet the conditions that support the use of the issue-rate cycle numbers. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 538: Scalar Load Instructions
Six cycles if operand forwarding is enabled. • Seven cycles if operand forwarding is not enabled. Additional cycles are required if the system performance does not match the above assumptions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 539: Scalar Store Instructions
Access to intermediate words consume one cycle for each word accessed. • Access to the trailing word consumes one cycle. Unused bytes are discarded if the trailing word is not aligned on a word boundary. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 540: Instruction Cache Misses
The address acknowledge is returned in the same cycle the data-cache unit asserts the PLB request. • The target instruction is returned in the cycle following the address acknowledge. Additional cycles are required if the system performance does not match the above assumptions. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 541: Powerpc ® 6Xx/7Xx Compatibility
Table E-1: 40x Registers Not Supported by 6xx/7xx Processors Name Description Purpose SPRG4–7 SPR general-purpose registers 4–7 Software defined USPRG0 User SPR general-purpose register 0 CCR0 Core-configuration register Processor configuration March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 542 External device control Data address register Exception and interrupt processing DSISR Data storage interrupt status register Decrementer Timer resources DABR Data-address breakpoint register Exception and interrupt processing IABR Instruction-address breakpoint register www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 543: Machine-State Register
FP—Floating-Point Available ME—Machine-Check Enable FE0—Floating-Point Exception-Mode 0 DWE—Debug Wait Enable SE—Single-Step Trace Enable DE—Debug Interrupt Enable BE—Branch Trace Enable FE1—Floating-Point Exception-Mode 1 Reserved Reserved IP—Exception Prefix IR—Instruction Relocate DR—Data Relocate Reserved March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 544: Processor-Version Register
• The MMU uses the page-translation tables to translate a 40-bit virtual address to a 32- bit physical address. The 40-bit virtual address is the combination of the 32-bit www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 545: Memory Protection
Memory Attributes Both the PowerPC 6xx/7xx and PowerPC 40x processors support the following memory attributes: • Write through (W). • Caching inhibited (I). March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 546: Cache Management
New save/restore registers (SRR2/SRR3) that support critical interrupts. The PowerPC 40x family uses the SRR0/SRR1 save/restore registers for noncritical interrupts, which are used for all interrupts in the PowerPC 6xx/7xx family. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 547: Timer Resources
• The programmable-interval timer (PIT) register. This register decrements at the same clock rate as the time base. Its function replaces that of the decrementer in the PowerPC 6xx/7xx family. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 548: Other Differences
The PowerPC 6xx/7xx family similarly implements power management using the MSR[POW] bit. PowerPC 7xx processors support four different power states, programmed using the HID0 register. Power management is disabled when an interrupt occurs. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 549: Powerpc ® Book-E Compatibility
PowerPC 40x family that are not defined by the PowerPC Book-E architecture. This table indicates whether or not a similar register with a different name and SPR number is defined by the PowerPC Book-E architecture. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 550 1012 IAC1 IAC2 1013 IAC2 IAC3 IAC3 IAC4 IAC4 USPRG0 SPRG8 Table F-3 summarizes the new registers defined by the PowerPC Book-E architecture or present in the PowerPC 440 processor. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 551 Reserved AP—Auxiliary Processor Available Implementation dependent 7:11 Reserved Reserved APE—APU Exception Enable WE—Wait State Enable CE—Critical Interrupt Enable Reserved Reserved: ILE—Interrupt Little Endian EE—External Interrupt Enable PR—Privilege Level FP—Floating-Point Available March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 552 The TLB invalidate all (tlbia) instruction is not supported by PowerPC Book-E processors because translation is always enabled. At least one valid TLB entry must exist—the entry that maps the TLB-miss interrupt handler. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 553 All memory attributes supported by PowerPC 40x processors can be used in real mode (address translation disabled) using storage-attribute control registers. These registers are not supported by PowerPC Book-E processors. March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 554: Memory Synchronization
PowerPC 40x processors. In the PowerPC 440 for example, an stwcx. to an unaligned memory operand yields a boundedly undefined result. In the PPC405, this operation causes an alignment exception. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 555 PowerPC 40x Function PowerPC Book-E Function MCI—Instruction Machine Check Implementation dependent Reserved PIL—Program, Illegal Instruction PPR—Program, Privileged Instruction PTR—Program, Trap Instruction PEU—Program, Unimplemented FP—Floating-Point Instruction Instruction DST—Data Storage, Store Instruction ST—Store March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 556 PowerPC Book-E processors support a common set of debug events on both instruction addresses and data addresses. Debug events are controlled using the DBCRn registers. Debug status is reported by the DBSR register. www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 557 See store instructions. core-configuration register cache programming guidelines debug events count leading-zeros branch taken (BT) instructions cache-control instructions count register DAC address-range match cache DAC exact-address match branching to access example March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 558 TLB miss debug internal-debug mode definition of See debug modes. external G storage attribute interrupt fixed-interval timer See storage attribute, guarded. See also exception. FPU unavailable www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 559 ID process ID register See cache, LRU. See PowerPC. process tag operand alignment processor reset alignment exception definition See reset. performance effects processor version register M storage attribute optional instructions March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 560 See synchronization, storage. timer-status register single stepping storage user-defined 0 register branches store instructions See also paging. exceptions byte reverse access sequential www.xilinx.com March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...
Page 561 See user-SPR general-purpose register. UTLB See TLB, unified TLB. See PowerPC. virtual memory virtual mode virtual page number W storage attribute See storage attribute, write through. wait state watchdog timer March 2002 Release www.xilinx.com Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778...
Page 562 March 2002 Release 1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation...