Non-Volatile Storage Through The Mpu Interface - Xilinx ML410 User Manual

Chapter 2: ML410 Embedded Development Platform
46
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The pinout shown in
programming solution. The J9 header is used when programming the FPGA by way of the
PC4 download cable.
Figure 2-12: PC4 JTAG Connector Pinout (J9)
The JTAG configuration port on the System ACE CF controller is connected directly to the
JTAG interface of the FPGA, as shown in
Table 2-14: JTAG Connection from System ACE CF to FPGA
Signal Name
FPGA_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS

Non-Volatile Storage through the MPU Interface

In addition to programming the FPGA and storing bitstreams, the System ACE CF
controller can be used to facilitate general-use, non-volatile storage. The System ACE CF
controller provides an MPU interface for allowing a microprocessor to access the
CompactFlash memory, enabling the use of the CompactFlash card as a file system. The
System ACE MPU interface is capable of supporting 16-bit or 8-bit modes of operation
because all 16 data lines are wired to the FPGA.
Table 2-15 shows the connection between the System ACE MPU interface and the FPGA.
Table 2-15: System ACE MPU Connection from FPGA to Controller
UCF Signal Name
SYSACE_FPGA_CLK
SYSACE_CLK_OE
SYSACE_MPA[0]
SYSACE_MPA[1]
SYSACE_MPA[2]
SYSACE_MPA[3]
SYSACE_MPA[4]
Figure 2-12 is compatible with the Parallel Cable IV (PC4) JTAG
GND
GND
GND
GND
13
J9
14
INIT
NC
PC4_TDI
SYSACE_TDO
Table 2-14.
System ACE Pin (U38)
80
81
82
85
FPGA Pin
Schematic Signal Name
(U37)
AF16 SYSACE_FPGA_CLK
AD4 SYSACE_CLK_OE
AE6 SYSACE_MPA[00]
AE4 SYSACE_MPA[01]
AE3 SYSACE_MPA[02]
AF6 SYSACE_MPA[03]
AF5 SYSACE_MPA[04]
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GND
GND
GND
1
2
VCC3V3
PC4_TMS
PC4_TCK
UG085_12_111505
FPGA Pin (U37)
AA14
W17
AA15
Y14
System ACE Pin
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
R
(U38)
93
77
70
69
68
67
45