Ddr And Ddr2 Memory; Ddr Component Memory - Xilinx ML410 User Manual

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DDR and DDR2 Memory

ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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ML410 platforms have two types of double data rate (DDR) memory, two component
DDRs and a DDR2 SDRAM DIMM. The two memory systems are independent and enable
users to build independent systems.

DDR Component Memory

The board contains 64 MB of DDR SDRAM (U42 and U43). Each chip is 16 bits wide and
together form a 32-bit data bus. All DDR SDRAM signals are terminated through 47Ω
resistors to a 1.25V VTT reference voltage. The board is designed for matched length traces
across all DDR control and data signals except clocks.
DDR Component Clock Signal
The DDR component clock signals are broadcast from the FPGA as a single differential pair
that drives both DDR chips. The delay on the clock trace is designed to match the delay of
the other DDR control and data signals. The DDR component clock is also fed back to the
FPGA to allow for clock deskew using Virtex-4 DCMs. The board is designed so that the
DDR clock signal reaches the FPGA clock feedback pin at the same time it arrives at the
DDR components. Figure 2-4
FPGA (U37)
CLKIN
CLK0
CLKFB
CLK90
DCM
CLKIN
CLKFB
IBUFG
LVCMOS
25
DDR_CLK_FB_in
DDR Component Signaling
The FPGA DDR interface uses SSTL2 signaling. All signals are controlled impedance and
are SSTL2 terminated.
is a block diagram of the DDR component interface.
BUFG
PLB_CLK
CLK90_IN
BUFG
BUFG
CLK0
DDR_CLK90_in
CLK90
Q
BUFG
DCM
Figure 2-4: DDR Component Block Diagram
www.xilinx.com
Detailed Description
FDDRSE
D0
D1 DDR_CLK
C0
SSTL2_I
C1
FDDRSE
D0
D1 DDR_CLK_N
C0
SSTL2_I
C1
C
CE
DQS_i
DDR_DQ/DQS
D
SSTL2_II
DDR2 x 2 (U42, U43)
UG085_05_113005
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