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Chapter 1: Introduction to Virtex-4, ISE, and EDK
PowerPC™ 405 Core
16
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♦
Built-in ChipSync™ source-synchronous technology
♦
Digitally-controlled impedance (DCI) active termination
♦
Fine grained I/O banking (configuration in one bank)
•
Flexible logic resources
•
Secure Chip AES bitstream encryption
•
90 nm copper CMOS process
•
1.2V core voltage
•
Flip-Chip packaging
•
RocketIO™ 622 Mb/s to 6.5 Gb/s multi-gigabit transceivers (MGT)
•
IBM PowerPC RISC processor core
♦
PowerPC 405 (PPC405) core
♦
Auxiliary processor unit interface (user coprocessor)
•
Multiple Tri-Mode Ethernet MACs
Table 1-1: Virtex-4 FX Family Members
Device
XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Logic Cells
12,312
PPC405
1
MGTs
N/A
Block RAM
648
(Kb)
XtremeDSP
32
Multipliers
•
32-bit Harvard architecture core
•
Five-stage execution pipeline
•
Integrated 16 KB level 1 instruction cache and 16 KB level 1 data cache
♦
Integrated level 1 cache parity generation and checking
•
CoreConnect™ bus architecture
•
Efficient, high-performance on-chip memory (OCM) interface to block RAM
•
PLB synchronization logic (enables non-integer CPU-to-PLB clock ratios)
•
Auxiliary Processor Unit (APU) interface and integrated APU controller
♦
Optimized FPGA-based coprocessor connection
♦
Automatic decode of PowerPC floating-point instructions
♦
Allows custom instructions (decode for up to eight instructions)
♦
Extremely efficient microcontroller-style interfacing
www.xilinx.com
19,224
41,904
56,880
1
2
8
12
16
1,224
2,592
4,176
32
48
128
ML410 Embedded Development Platform
94,896
142,128
2
2
2
20
24
6,768
9,936
160
192
UG085 (v1.7.2) December 11, 2008
R
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