Gpio Connector (J5); System Management Bus Controller - Xilinx ML410 User Manual

Chapter 2: ML410 Embedded Development Platform
66
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GPIO Connector (J5)

There are 15 GPIO pins connecting the ALi M1535D+ to the 24-pin GPIO header (J5). These
can be accessed through the ALi M1535D+ by way of the PCI bus.
types and number of GPIO signals available to the user from the ALi South Bridge.
Table 2-30: Type of GPIO Available on Header J5
ALi GPIO Types
Output
Input
Input/Output
Table 2-31 shows the connections from the ALi, M1535D+, GPIO signals available at the
GPIO header (J5).
Table 2-31: GPIO Connections on Header J5
Schematic Net
Name
GPO_10
GPO_29
GPO_30
GPO_34
GPO_35
GPI_24
GPI_25
GPI_34
GPI_36
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_22
GPIO_23

System Management Bus Controller

The SMBus host controller in the M1535D+ supports the ability to communicate with
power-related devices using the SMBus protocol. It provides quick send byte/receive
byte/ write byte/write word/read word/block read/block write command with clock
synchronization function and 10-bit addressing ability. See
69 for more information regarding the devices that are connected to the SMBus.
Number
Available
5
4
6
M1535D+
GPIO Pin (J5)
(U15)
21 T3
23 N17
20 N18
22 P18
24 P19
1 M17
3 E9
5 W7
7 U8
9 Y3
11 V4
13 W4
15 Y4
17 U6
19 U5
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Table 2-30
I/O Type
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
"IIC/SMBus Interface," page
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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shows the