Cpu Jtag Header Pinout; Cpu Jtag Connection To Fpga - Xilinx ML410 User Manual

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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Table 2-19: CPU Trace/Debug Connection to FPGA (Cont'd)
Pin Name
ATD_8
TRC_TS6

CPU JTAG Header Pinout

Figure 2-15 shows J12, the 16-pin header that can be used to debug the software operating
in the CPU with debug tools such as Parallel Cable IV or third party tools. Refer to the
PowerPC 405 Processor Block Reference Guide
debug port signals.

CPU JTAG Connection to FPGA

The connection between the CPU JTAG header (J12) and the FPGA are shown in
Table 2-20. These are attached to the PPC405 JTAG debug resources using normal FPGA
routing resources. The JTAG debug resources are not hard-wired to particular pins and are
available for attachment in the FPGA fabric, making it possible to route these signals to the
preferred FPGA pins.
Table 2-20: CPU JTAG Connection to FPGA
Pin Name
CPU_TDO
CPU_TDI
CPU_TRST_N
CPU_TCK
CPU_TMS
CPU_HALT_N
FPGA Pin (U37)
AJ7
AE12
[Ref 1]
CPU_TMS
CPU_HALT_N
J12
15
16
GND
Figure 2-15: CPU JTAG Header (J12)
FPGA Pin (U37)
AM8
AK29
AH27
AJ27
AM7
AH17
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Detailed Description
Connector Pin (P8)
37
38
for more information on the JTAG
CPU_TCK
CPU_TDI
CPU_TDO
1
2
CPU_TRST_N
CPU_VSENSE
UG085_15_111505
Connector Pin (J12)
1
3
4
7
9
11
53