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Chapter 2: ML410 Embedded Development Platform
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Table 2-4: Connections from FPGA to DDR1 SDRAMs (U42 and U43) (Cont'd)
UCF Signal Name
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]
DDR1_A[13]
DDR2 SDRAM DIMM
The DDR2 DIMM is a standard 240-pin DIMM socket, supporting standard computer
DDR2 memory.
ML410 platforms are shipped with a single-rank registered 256 MB PC2-3200 DDR2-400
Dual Inline Memory Module (DIMM). The DDR2 DIMM is commercially available from
Wintec Industries as part number WID32M72R8 (-5 speed grade). The DDR2 DIMM uses
nine 32M x 8 DDR2 SDRAM devices with 14-row address lines, 10-column address lines,
and two bank address lines. Read and write access is programmable in burst lengths of 4 or
8. The memory module inputs and outputs are compatible with SSTL18 signaling. Serial
Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also supported. See
the
"IIC/SMBus Interface"
EEPROM.
The DDR2 DIMM memory interface includes a 64-bit wide datapath to the DDR2 DIMM,
thus ECC is not supported.
DDR2 Memory Expansion
The DDR2 interface is very flexible and can accommodate different DDR2 memory
requirements, such as increased memory size. The DDR2 interface core delivered with
EDK supports registered DRR2 memory interfaces. Please review the EDK Processor IP
User Guide
[Ref 2]
when migrating to a different DDR2 DIMM.
DDR2 Clock Signal
The DDR2 clock signal is broadcast from the FPGA as a single differential pair that drives
a clock fan-out chip, which then drives the DDR2 DIMM. The clock fan-out chip provides
support for registered DIMMs. The delay on the clock trace is designed to match the delay
of the other DDR2 control and data signals. The DDR2 clock is also fed back to the FPGA
to allow for clock deskew using Virtex-4 DCMs. The board is designed so that the DDR2
clock signal reaches the FPGA clock feedback pin at the same time as it arrives at the DDR2
DIMM.
DDR2 Signaling
All DDR2 SDRAM signals are terminated through 47Ω resistors to a 0.9V VTT reference
voltage. The board is designed for matched length traces across all DDR2 control and data
signals, except clocks. The FPGA DDR2 interface supports SSTL18 signaling. All DDR2
signals are controlled impedance and are SSTL18 terminated.
XC4FX60 Pin
Schematic Signal
(U37)
Name
K23
DDR1_A[9]
K24
DDR1_A[10]
K26
DDR1_A[11]
J24
DDR1_A[12]
E16
DDR1_A[13]
section for more details on accessing the DIMM module's SPD
www.xilinx.com
ML410 Embedded Development Platform
DDR1
DDR1
SDRAM
SDRAM
(U42)
(U43)
40
40
28
28
41
41
42
42
17
17
UG085 (v1.7.2) December 11, 2008
R
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