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Xilinx LogiCORE MicroBlaze Product Manual

Xilinx LogiCORE MicroBlaze Product Manual

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LogiCORE IP
MicroBlaze Micro
Controller System v1.3
Product Guide
PG048 December 18, 2012

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Summary of Contents for Xilinx LogiCORE MicroBlaze

  • Page 1 LogiCORE IP MicroBlaze Micro Controller System v1.3 Product Guide PG048 December 18, 2012...

  • Page 2: Table Of Contents

    Required Constraints ............. . 32 MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 3 Xilinx Software Development Kit ........

  • Page 4: Section I: Summary

    SECTION I: SUMMARY IP Facts Overview Product Specification Designing with the Core MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 5 Design Entry Vivado Design Suite 2012.4 • MicroBlaze processor Mentor Graphics ModelSim Simulation • Local Memory Vivado Simulator Xilinx Synthesis Technology (XST) Synthesis • MicroBlaze Debug Module (MDM) Vivado Synthesis • Tightly Coupled I/O Module including Support Provided by Xilinx @ www.xilinx.com/support...

  • Page 6: Chapter 1: Overview

    Feature Summary MicroBlaze The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs). Detailed information on the MicroBlaze processor can be found in the MicroBlaze Processor Reference Guide...

  • Page 7: Licensing And Ordering Information

    Table 4-3. Licensing and Ordering Information This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado™ Design Suite and ISE® Design Suite tools under the terms of the Xilinx End User License.

  • Page 8: Chapter 2: Product Specification

    Chapter 2 Product Specification Standards Compliance The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx® Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series FPGAs Configuration User Guide [Ref 10].

  • Page 9: Resource Utilization

    Table 2-2: Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156) Parameter Values (other parameters at default value) Device Resources LUTs Flip-Flops 65000 65000 65000 65000 65000 65000 MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 10: Port Descriptions

    Byte enables for access IO_Write_Data 31:0 Data to write for I/O Bus write access IO_Read_Data 31:0 Read data for I/O Bus read access IO_Ready Ready handshake to end I/O Bus access MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 11: Register Space

    Local Memory for MicroBlaze software C_MEMSIZE - 0x7FFFFFFF Reserved 0x80000000 - 0x800000FF I/O Module Mapped to I/O Module registers 0x80000100 - 0xBFFFFFFF Reserved 0xC0000000 - 0xFFFFFFFF I/O Bus Mapped to I/O Bus address output MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 12: Chapter 3: Designing With The Core

    MicroBlaze Trace signals. The Trace signals are directly connected to the MicroBlaze processor inside the MicroBlaze MCS. MicroBlaze Debug Module See the Xilinx SDK Help [Ref 6] and the MicroBlaze Debug Module Product Guide [Ref 3] a description of debugging with the MicroBlaze Debug Module (MDM).

  • Page 13: Resets

    Resets The Reset input is the master reset input signal for the entire MicroBlaze MCS. In addition, the entire MicroBlaze MCS or just the MicroBlaze processor can be reset from the Xilinx MicroProcessor Debugger (XMD), provided that debug is enabled.

  • Page 14: Section Ii: Vivado Design Suite

    SECTION II: VIVADO DESIGN SUITE Customizing and Generating the Core Constraining the Core MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 15: Chapter 4: Customizing And Generating The Core

    Chapter 4 Customizing and Generating the Core This chapter includes information on using Xilinx tools to customize and generate the core using the Vivado™ Design Suite. MicroBlaze™ MCS parameters are divided in seven tabs: MCS, UART, FIT, PIT, GPO, GPI and Interrupts.
  • Page 16 Enable I/O Bus - Enables I/O Bus port. • Enable Debug Support - When debug support is enabled, it is possible to debug software via JTAG, from Xilinx Software Development Kit (SDK) or directly using the Xilinx Microprocessor Debugger (XMD). •...
  • Page 17 This error can be a framing error, an overrun error or a parity error (if parity is used), When the interrupt is not enabled the UART must be polled to check if an error has occurred after a character has been received. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 18 Use FIT - Enable the Fixed Interval Timer. • Number of Clocks Between Strobes - The number of clock cycles between each strobe. • Generate Interrupt - Generate an interrupt for each Fixed Interval Timer strobe. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 19 Interval Timer or Fixed Interval Timer can be used as prescaler, as well as a dedicated external enable input. • Generate Interrupt - Generate an interrupt when the Programmable Interval Timer has counted down to zero. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 20 Initial Value of GPO - Set the initial value of the General Purpose Output port. The right most bit in the value is assigned to bit 0 of the port, the next right most to bit 1, and so on. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 21 Use GPI - Enable the General Purpose Input port. • Number of Bits - Set the number of bits of the General Purpose Input port. • Generate Interrupt - Generate an interrupt when a General Purpose Input changes. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 22 When a bit is set to one, high level or rising edge is used, otherwise low level or falling edge is used. • Use Low-latency Interrupt Handling - Enable the use of low-latency interrupt handling. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 23: Parameter Values

    Enable implementation of 0 = Not Used Integer debug 1 = Used C_JTAG_CHAIN Select JTAG user-defined 1 = USER1 register 2 = USER2 Integer 3 = USER3 4 = USER4 MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 24 0 = Not Used integer 1 = Used C_PITx_SIZE Size of PITx counter 1 - 32 integer C_PITx_READABLE Make PITx counter software 0 = Not SW readable readable integer 1 = SW readable MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 25 1. Values automatically populated by tool. 2. x=1, 2, 3 or 4. 3. Selecting PIT prescaler the same as PITx is illegal; for example, PIT2 cannot be prescaler to itself. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 26 Enable use of instructions: MSRSET and MSRCLR C_USE_PCMP_INSTR Enable use of instructions: CLZ, PCMPBF, PCMPEQ, and PCMPNE C_USE_REORDER_INSTR Enable use of instructions: LBUR, LHUR, LWR, SBR,SHR, SWR, SWAPB, and SWAPH MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 27 LMB I/O Module register base address 0x80000000 C_HIGHADDR LMB I/O Module register high address 0x8000FFFF C_MASK LMB I/O Module register address space decode mask 0xC0000000 C_IO_HIGHADDR LMB I/O Module I/O bus base address 0xC0000000 MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 28 LMB address bus width C_LMB_DWIDTH LMB data bus width C_ECC Implement error correction and detection 0 = No ECC All other ECC as well AXI and PLB parameters are don’t care MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 29: Parameter - Port Dependencies

    Table 4-9: Parameter-Port Dependencies Parameter Name Ports (Port width depends on parameter) C_INTC_INTR_SIZE INTC_Interrupt C_GPO1_SIZE GPO1 C_GPO2_SIZE GPO2 C_GPO3_SIZE GPO3 C_GPO4_SIZE GPO4 C_GPI1_SIZE GPI1 C_GPI2_SIZE GPI2 C_GPI3_SIZE GPI3 C_GPI4_SIZE GPI4 MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 30: Tool Flow

    Associate ELF Files Implement Project Generate Import Bitstream Bitstream (toplevel.bit) Hardware Implementation Simulate Download and Run Download and Run Software or Debug Software Software Figure 4-8: Generic Vivado Tool Flow MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 31 The MicroBlaze MCS configuration is available in the generated file microblaze_0/include/xparameters.h. • Import Hardware Implementation: Select Xilinx Tools > Program FPGA in the menu. ° Click the first Browse button, and navigate to the bitstream: ° MicroBlaze Micro Controller System v1.3 www.xilinx.com...
  • Page 32 MicroBlaze MCS component, the merged BMM file updated with block RAM placement must be selected instead. Click Program to perform the import and program the FPGA. ° For additional information, see the Xilinx SDK Help [Ref MicroBlaze Micro Controller System v1.3 www.xilinx.com...

  • Page 33: Chapter 5: Constraining The Core

    MicroBlaze MCS is fully synchronous with all clocked elements clocked by the Clk input. Clock Placement There are no specific Clock placement requirements for this core. Banking There are no specific Banking rules for this core. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 34: Transceiver Placement

    Chapter 5: Constraining the Core Transceiver Placement There are no Transceiver Placement requirements for this core. I/O Standard and Placement There are no specific I/O standards and placement requirements for this core. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 35: Section Iii: Ise Design Suite

    SECTION III: ISE DESIGN SUITE Customizing and Generating the Core Constraining the Core MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 36: Chapter 6: Customizing And Generating The Core

    Chapter 6 Customizing and Generating the Core This chapter includes information on using Xilinx tools to customize and generate the core using the ISE® Design Suite. The I/O Module parameters are divided in seven tabs: MCS, UART, FIT, PIT, GPO, GPI and Interrupts.
  • Page 37 Enable I/O Bus - Enables I/O Bus port. • Enable Debug Support - When debug support is enabled, it is possible to debug software via JTAG, from Xilinx Software Development Kit (SDK) or directly using the Xilinx Microprocessor Debugger (XMD). •...
  • Page 38 This error can be a framing error, an overrun error or a parity error (if parity is used), When the interrupt is not enabled the UART must be polled to check if an error has occurred after a character has been received. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 39 Use FIT - Enable the Fixed Interval Timer. • Number of Clocks Between Strobes - The number of clock cycles between each strobe. • Generate Interrupt - Generate an interrupt for each Fixed Interval Timer strobe. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 40 Interval Timer or Fixed Interval Timer can be used as prescaler, as well as a dedicated external enable input. • Generate Interrupt - Generate an interrupt when the Programmable Interval Timer has counted down to zero. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 41 Initial Value of GPO - Set the initial value of the General Purpose Output port. The right most bit in the value is assigned to bit 0 of the port, the next right most to bit 1, and so on. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 42 Use GPI - Enable the General Purpose Input port. • Number of Bits - Set the number of bits of the General Purpose Input port. • Generate Interrupt - Generate an interrupt when a General Purpose Input changes. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 43 When a bit is set to one, high level or rising edge is used, otherwise low level or falling edge is used. • Use Low-latency Interrupt Handling - Enable the use of low-latency interrupt handling. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 44: Parameter Values

    For a brief description of the SDK software flow see SDK in Chapter Generic PlanAhead and Project Navigator Tool Flow The generic tool flow in PlanAhead and Project Navigator is shown in Figure 6-8. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 45 PlanAhead or Project Navigator, and the relationship between the hardware and software tools. Each of the steps are described in general here. Specific commands used in PlanAhead, ISE Project Navigator and Xilinx Software Development Kit (SDK) are covered in the following sections. •...
  • Page 46 The step can be performed by invoking the microblaze_mcs_data2mem Tcl procedure, with one argument for each MicroBlaze MCS component in the project, MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 47 To perform the step manually, see the specific commands for PlanAhead or ISE Project Navigator below. • Download and Run Software: When downloading the updated bitstream to the FPGA with impact, the software immediately starts to run as soon as reset is deactivated. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 48 [current_run] -program ngdbuild -option {More Options} -value \ {-bm /project-path/project-name.srcs/sources_1/ip/component-name/ component-name_bd.bmm} With more than one MicroBlaze MCS component, the -bm option must indicate the merged BMM file instead. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 49 Here part is the complete part name, consisting of device, package, and speed concatenated. For each additional MicroBlaze MCS component, the -bd option has to be repeated, followed by the appropriate executable ELF file, the keyword tag, and the component name. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 50 Chapter 6: Customizing and Generating the Core If the output directory indicated by the -bx option does not exist, it has to be created manually. For additional information, see the Xilinx PlanAhead Manuals [Ref Project Navigator The Project Navigator commands to achieve the MicroBlaze MCS specific steps above are detailed here.
  • Page 51 For each additional MicroBlaze MCS component, the -bd option has to be repeated, followed by the appropriate executable ELF file, the keyword tag, and the component name. For additional information, see the Xilinx ISE Manuals [Ref MicroBlaze Micro Controller System v1.3 www.xilinx.com...

  • Page 52: Chapter 7: Constraining The Core

    Chapter 7 Constraining the Core Clock Management MicroBlaze MCS is fully synchronous with all clocked elements clocked by the Clk input. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 53: Section Iv: Appendices

    SECTION IV: APPENDICES Application Software Development Debugging Additional Resources MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 54: Appendix A: Application Software Development

    Appendix A Application Software Development Xilinx Software Development Kit MicroBlaze MCS can be used with the Xilinx Software Development Kit (SDK), in the same way as any embedded system. The specific steps needed with MicroBlaze MCS are described in SDK in Chapter...

  • Page 55: Appendix B: Debugging

    Appendix B Debugging This appendix includes details about resources available on the Xilinx Support website and debugging tools. In addition, this appendix provides a step-by-step debugging process to guide you through debugging the MicroBlaze MCS core. The following topics are included in this appendix: •...
  • Page 56 Known Issues Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 57: Debug Tools

    Reference Boards All Xilinx development boards support MicroBlaze MCS. These boards can be used to prototype designs and establish that the core can communicate with the system. Troubleshooting This section provides help in diagnosing and correcting issues that can occur with the MicroBlaze™...
  • Page 58 (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 59 • Ensure that the file extension is correct. • Ensure that each path is enclosed in double quotes if it includes space characters. • The path separator character must be /. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...
  • Page 60 ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb in library work failed ** Fatal: (vsim-7) Failed to open VHDL file "component-name.lmb_bram_index.mem" in r mode. Possible causes: The MEM files have not been generated. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 61: Simulation Debug

    The simulation debug flow for ModelSim is described below. A similar approach can be used with other simulators. • Check for the latest supported versions of ModelSim in the Xilinx Design Tools: Release Notes Guide. Is this version being used? If not, update to this version. •...

  • Page 62: Hardware Debug

    PCB issue. Ensure that all clock sources are active and clean. • If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the LOCKED port. MicroBlaze Micro Controller System v1.3 www.xilinx.com PG048 December 18, 2012...

  • Page 63: Appendix C: Additional Resources

    For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at: www.xilinx.com/support. For a glossary of technical terms used in Xilinx documentation, see: www.xilinx.com/company/terms.htm. References These documents provide supplemental material useful with this user guide: 1.

  • Page 64: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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