Xilinx ML410 User Manual page 76

Chapter 2: ML410 Embedded Development Platform
76
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SW3
Shown here with
ON
CFGADDR[2:0]
System ACE CFG
set to 000 (default)
ON => SW Closed
CFGADDR[2:0] =
0x0
Default
0x4
Figure 2-21: SW3: System ACE Configuration Switch Detail
MGT Clock Source Select (SW6)
SW6 is a three-position DIP switch that controls the select lines of the clock multiplexer at
U6, as shown in Figure 2-3, page
associated SEL0 and SEL1 bits are set to a logic 1. When the switches are in the OFF
position, the select lines are pulled down to ground (Logic 0). To control the select lines
from the FPGA, switches 1 and 2 must be set to the open (OFF) position to prevent
contention. Switch position 3 is not used.
Table 2-39: SW6 Output
Signal Name
CLK_SEL0
CLK_SEL0
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2.5V
System ACE (U38)
RESET
SYSACE_RESET_N
0x1 0x2 0x3
0x5 0x6 0x7
27. When switches 1 and 2 are in the ON position, the
Table 2-39 shows the pinout for the select lines.
FPGA Pin (U37)
AG16
AG17
ML410 Embedded Development Platform
SW1
U31
Debounce
System ACE
Reset
UG085_20_120505
Description
Select 0
Select 1
UG085 (v1.7.2) December 11, 2008
R