User Manuals: Xilinx Virtex-II Pro PPC405 Kit

Manuals and User Guides for Xilinx Virtex-II Pro PPC405 Kit. We have 1 Xilinx Virtex-II Pro PPC405 Kit manual available for free PDF download: User Manual

Xilinx Virtex-II Pro PPC405 User Manual (563 pages)

Platform FPGA Developer's Kit

Brand: Xilinx | Category: Microcontrollers | Size: 4 MB

Instruction Fields
5
Pseudocode Conventions
7
Operator Precedence
9
Additional Reading
13
Introduction to the PPC405
15
Powerpc Architecture Overview
15
Powerpc Architecture Levels
16
Powerpc Embedded-Environment Architecture
18
Powerpc Book-E Architecture
21
PPC405 Features
21
Privilege Modes
22
Address Translation Modes
23
Addressing Modes
23
Data Types
23
Register Set Summary
24
PPC405 Organization
26
Operational Concepts
33
Execution Model
33
Synchronization Operations
34
Context Synchronization
34
Execution Synchronization
34
Storage Synchronization
35
Processor Operating Modes
35
Privileged Mode
35
User Mode
36
Memory Organization
36
Effective-Address Calculation
36
Physical Memory
37
Memory Management
37
Operand Conventions
39
Byte Ordering
41
Operand Alignment
45
Instruction Conventions
46
Instruction Forms
46
Instruction Classes
47
Powerpc Book-E Instruction Classes
49
User Programming Model
51
User Registers
51
Special-Purpose Registers (Sprs)
52
General-Purpose Registers (Gprs)
52
Condition Register (CR)
53
Fixed-Point Exception Register (XER)
55
Link Register (LR)
55
Count Register (CTR)
56
User-SPR General-Purpose Register
56
SPR General-Purpose Registers
57
Exception Summary
58
Branch and Flow-Control Instructions
59
Conditional Branch Control
59
Branch Prediction
62
Branch-Target Address Calculation
64
Condition-Register Logical Instructions
68
System Call
68
System Trap
69
Integer Load and Store Instructions
70
Operand-Address Calculation
70
Load Instructions
73
Store Instructions
76
Load and Store with Byte-Reverse Instructions
77
Load and Store Multiple Instructions
78
Load and Store String Instructions
79
Integer Instructions
81
Arithmetic Instructions
82
Logical Instructions
87
Rotate Instructions
91
Shift Instructions
95
Multiply-Accumulate Instruction-Set Extensions
97
Modulo and Saturating Arithmetic
97
Multiply-Accumulate Instructions
98
Negative Multiply-Accumulate Instructions
105
Multiply Halfword to Word Instructions
111
Floating-Point Emulation
114
Processor-Control Instructions
114
Condition-Register Move Instructions
115
Special-Purpose Register Instructions
116
Synchronizing Instructions
116
Implementation of Eieio and Sync Instructions
117
Synchronization Effects of Powerpc Instructions
117
Semaphore Synchronization
118
Memory-Control Instructions
119
Special-Purpose Registers
123
Machine-State Register
123
Processor-Version Register
125
Privileged Instructions
126
System Linkage
126
Processor Wait State
128
Memory-System Management
129
Memory-System Organization
129
Memory-System Features
130
Cache Organization
130
Instruction-Cache Operation
133
Data-Cache Operation
135
Data-Cache Performance
137
Accessing Memory
139
Memory Coherency
140
Atomic Memory Access
140
Ordering Memory Accesses
140
Preventing Inappropriate Speculative Accesses
141
Memory-System Control
143
Storage-Attribute Control Registers
144
Cache Control
148
Cache Instructions
148
Core-Configuration Register
151
Software Management of Cache Coherency
155
How Coherency Is Lost
155
Enforcing Coherency with Software
157
Self-Modifying Code
159
Cache Debugging
160
Icread Instruction
160
Dcread Instruction
161
Real Mode
163
Virtual-Memory Management
163
Virtual Mode
164
Process-ID Register
166
Page-Translation Table
166
Translation Look-Aside Buffer
167
TLB Entries
168
TLB Access
171
TLB-Access Failures
172
Virtual-Mode Access Protection
174
TLB Access-Protection Controls
174
Zone Protection
174
Effect of Access Protection on Cache-Control Instructions
175
UTLB Management
177
Recording Page Access and Page Modification
178
Maintaining Shadow-TLB Consistency
179
Exceptions and Interrupts
181
Synchronous and Asynchronous Exceptions
182
Precise and Imprecise Interrupts
182
Partially-Executed Instructions
182
PPC405D5 Exceptions and Interrupts
183
Critical and Noncritical Exceptions
184
Transferring Control to Interrupt Handlers
184
Returning from Interrupt Handlers
186
Simultaneous Exceptions and Interrupt Priority
187
Persistent Exceptions and Interrupt Masking
188
Interrupt-Handling Registers
189
Machine-State Register Following an Interrupt
189
Exception-Vector Prefix Register
192
Exception-Syndrome Register
192
Data Exception-Address Register
194
Interrupt Reference
194
Critical-Input Interrupt (0X0100)
195
Machine-Check Interrupt (0X0200)
196
Data-Storage Interrupt (0X0300)
198
Instruction-Storage Interrupt (0X0400)
200
External Interrupt (0X0500)
201
Alignment Interrupt (0X0600)
202
Program Interrupt (0X0700)
203
FPU-Unavailable Interrupt (0X0800)
205
System-Call Interrupt (0X0C00)
206
APU-Unavailable Interrupt (0X0F20)
207
Programmable-Interval Timer Interrupt (0X1000)
208
Fixed-Interval Timer Interrupt (0X1010)
209
Watchdog-Timer Interrupt (0X1020)
210
Data TLB-Miss Interrupt (0X1100)
211
Instruction TLB-Miss Interrupt (0X1200)
212
Debug Interrupt (0X2000)
213
Timer Resources
215
Reading and Writing the Time Base
217
Computing Time of Day
218
Timer-Event Registers
219
Programmable-Interval Timer Register
219
Timer-Control Register
220
Timer-Status Register
221
Timer-Event Interrupts
221
Watchdog-Timer Events
222
Programmable-Interval Timer Events
224
Fixed-Interval Timer Events
225
Debug Modes
228
Internal-Debug Mode
228
External-Debug Mode
228
Debug Registers
229
Debug-Wait Mode
229
Real-Time Trace-Debug Mode
229
Debug-Control Registers
230
Debug-Status Register
233
Instruction Address-Compare Registers
234
Debug Events
235
Data Address-Compare Registers
235
Data Value-Compare Registers
235
Instruction-Complete Debug Event
237
Branch-Taken Debug Event
238
Exception-Taken Debug Event
238
Trap-Instruction Debug Event
238
Unconditional Debug Event
239
Instruction Address-Compare Debug Event
239
Data Address-Compare Debug Event
241
Data Value-Compare Debug Event
245
Imprecise Debug Event
248
Freezing the Timers
248
Debug Interface
249
JTAG Debug Port
249
JTAG Connector
249
Reset and Initialization
253
Processor State after Reset
253
First Instruction
255
Sample Initialization Code
257
Instruction Set
261
Instruction Encoding
262
Split-Field Notation
263
Alphabetical Instruction Listing
263
Register Summary
459
Register Cross-Reference
459
General-Purpose Registers
460
Machine-State Register and Condition Register
462
Special-Purpose Registers
462
Time-Base Registers
467
Device Control Registers
467
Instruction Summary
469
Instructions Sorted by Mnemonic
469
Instructions Sorted by Opcode
473
Instructions Grouped by Function
478
Instructions Grouped by Form
484
Instruction Set Information
489
List of Mnemonics and Simplified Mnemonics
494
Simplified Mnemonics
513
Branch Instructions
513
True/False Conditional Branches
513
Comparison Conditional Branches
516
Branch Prediction
519
Compare Instructions
520
CR-Logical Instructions
520
Rotate and Shift Instructions
521
Subtract Instructions
523
TLB-Management Instructions
524
Trap Instructions
524
Other Simplified Mnemonics
526
Move to Condition Register
527
Programming Considerations
529
Synchronization Examples
529
Compare and Swap
531
Lock Acquisition and Release
531
List Insertion
532
Multiple-Precision Shifts
532
Code Optimization Guidelines
534
Conditional Branches
534
Cache Usage
535
Instruction Performance
536
General Rules
536
Scalar Load Instructions
538
Scalar Store Instructions
539
String and Multiple Instructions
539
Instruction Cache Misses
540
Powerpc ® 6Xx/7Xx Compatibility
541
Machine-State Register
543
Processor-Version Register
544
Memory Management
544
Memory Translation
544
Memory Protection
545
Memory Attributes
545
Cache Management
546
Timer Resources
547
Other Differences
548
Powerpc ® Book-E Compatibility
549
Memory Synchronization
554

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User Manuals: Xilinx Virtex-II Pro PPC405 Kit

Xilinx Virtex-II Pro PPC405 User Manual (563 pages)

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