Xilinx ML410 User Manual page 36

Chapter 2: ML410 Embedded Development Platform
36
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Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont'd)
UCF Signal Name
DDR2_DQ[43]
DDR2_DQ[44]
DDR2_DQ[45]
DDR2_DQ[46]
DDR2_DQ[47]
DDR2_DQ[48]
DDR2_DQ[49]
DDR2_DQ[50]
DDR2_DQ[51]
DDR2_DQ[52]
DDR2_DQ[53]
DDR2_DQ[54]
DDR2_DQ[55]
DDR2_DQ[56]
DDR2_DQ[57]
DDR2_DQ[58]
DDR2_DQ[59]
DDR2_DQ[60]
DDR2_DQ[61]
DDR2_DQ[62]
DDR2_DQ[63]
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XC4FX60 Pin Schematic Signal
(U37) Name
Y31 DDR2_DQ[43]
AA31 DDR2_DQ[44]
AB31 DDR2_DQ[45]
AD31 DDR2_DQ[46]
AB28 DDR2_DQ[47]
AF31 DDR2_DQ[48]
U30 DDR2_DQ[49]
V30 DDR2_DQ[50]
Y26 DDR2_DQ[51]
AA30 DDR2_DQ[52]
AB30 DDR2_DQ[53]
AC30 DDR2_DQ[54]
AD30 DDR2_DQ[55]
AF30 DDR2_DQ[56]
V29 DDR2_DQ[57]
W29 DDR2_DQ[58]
Y29 DDR2_DQ[59]
AA29 DDR2_DQ[60]
AC29 DDR2_DQ[61]
AD29 DDR2_DQ[62]
AE29 DDR2_DQ[63]
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
R
DDR2 DIMM
(P48)
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236