Xilinx ML410 User Manual page 78

Chapter 2: ML410 Embedded Development Platform
78
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Table 2-41 shows the signals available at the front panel interface header (J23).
Table 2-41: Front Panel Interface Connector (J23)
J23
Schematic Signal
Pin
1 SYACE_CFGA0
2 FPGA_LED_USER1
3 SYACE_CFGA1
4 FPGA_LED_USER2
5 SYACE_CFGA2
6 NC
7 LED_DONE_R
8 GND
9 ATX_PWRLED
10 ATX_SPKR
11 SCL
12 SCA
13 GND
14 GND
15 KBINH
16 VCC5V
17 ATX_IDELED_R
18 VCC5V
19 GND
20 ATX_PWR_TOG
21 PB_SYSACE_RESET
22 GND
23 PB_FPGA_CPU_RESET
24 GND
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Description
Used to select System ACE configuration, CFGADDR0
User defined function, connects to the FPGA, U37-G15,
(2.5V bank)
Used to select System ACE configuration, CFGADDR1
User defined function, connects to the FPGA, U37-G16,
(2.5V bank)
Used to select System ACE configuration, CFGADDR2
No Connect
Remote FPGA DONE indicator; tie this pin to anode of
user's LED and cathode to ground
Ground
ATX 3.3V power indicator; tie this pin to anode of user's
LED and cathode to ground
Used to drive user-provided ATX speaker
IIC bus
IIC bus
Ground
Ground
Tie this pin to ground to activate Keyboard Inhibit (See
ALi M1536D+ data sheet for more details)
5V ATX power available to user
ATX IDE access indicator; tie this pin to anode of user's
LED and cathode to ground
5V ATX power available to user
Ground
ATX power toggle
Used to reset System ACE when driven Low, as
described in "System ACE Reset (SW1)"
Ground
Used to reset CPU when driven Low, as described in
"CPU Reset (SW2)"
Ground
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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