Xilinx ML410 User Manual page 99

R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Downloaded from Elcodis.com electronic components distributor
Table A-2 describes the MGT and SATA clock connections for earlier board revisions.
Table A-2: MGT and SATA Clock Connections for Revisions C and D
Schematic Net Name
SGMIICLK_Q0
SGMIICLK_NQ0
MGTCLK_P_110
MGTCLK_N_110
SATACLK_Q0
SATACLK_NQ0
Notes:
5. These clocks are differential pairs through the RocketIO transceivers and are not available on ML410-P
boards. See Figure A-1, page
www.xilinx.com
Clock
FPGA Pin (U37)
Source
(Fixed) M34
(Fixed) N34
(Fixed) AP3
(Fixed) AP4
(Fixed) AP29
(Fixed) AP28
98.
(1)
Description
SMA or onboard 125 MHz clock
source selectable through SW6.
SMA or onboard 125 MHz clock
source selectable through SW6.
SMA or onboard 125 MHz clock
source selectable through SW6.
SMA or onboard 125 MHz clock
source selectable through SW6.
150 MHz Serial ATA clock.
150 MHz Serial ATA clock.
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