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R
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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support the attachment of debug tools. These enhancements comply with the IEEE 1149.1
specifications for vendor-specific extensions and are compatible with standard JTAG
hardware for boundary-scan system testing.
The PPC405 JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI,
and TDO. It also implements the optional TRST signal. The frequency of the JTAG clock
signal can range from 0 MHz (DC) to one-half of the processor clock frequency. The JTAG
debug port logic is reset at the same time the system is reset, using TRST. When TRST is
asserted, the JTAG TAP controller returns to the test-logic reset state. See the PowerPC 405
Processor Block Reference Guide
signals.
Figure 2-14
shows a 38-pin Mictor connector that combines the CPU Trace and the CPU
Debug interfaces for high-speed, controlled-impedance signaling. For more information
on starting and stopping the processor, single-stepping instruction execution on the trace-
debug capabilities, how trace-debug works, and how to connect an external trace tool, see
the RISCWatch Debugger User's Guide.
TRC_TS6
TRC_TS5
TRC_TS4
TRC_TS3
TRC_TS2E
TRC_TS1E
TRC_TS2O
TRC_TS1O
ATD 16
ATD 17
2.5V
ATD 18
NC
NC
TRC_VSENSE
NC
NC
TRC_CLK
NC
NC
Figure 2-14: Combined Trace/Debug Connector Pinout
Table 2-19
shows the CPU trace/debug connections from P8 to the FPGA.
Table 2-19: CPU Trace/Debug Connection to FPGA
Pin Name
-
-
-
-
www.xilinx.com
[Ref 1]
for more information on the JTAG debug port
Mictor 38 (P8)
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND, G1, G2, G3, G4, G5
FPGA Pin (U37)
NC
NC
NC
NC
Detailed Description
37
ATD_8
35
ATD_9
33
ATD_10
31
ATD_11
29
ATD_12
27
ATD_13
25
ATD_14
23
ATD_15
21
CPU_TRST_N
19
CPU_TDI
17
CPU_TMS
15
CPU_TCK
13
NC
11
CPU_TDO
9
NC
7
CPU_HALT_N
5
ATCB_CLK
3
NC
1
NC
UG085_14_120405
Connector Pin (P8)
1
2
3
4
51
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